Read Cycles - Buffer Miss - STMicroelectronics SPC572L series Reference Manual

Flash memory controller (PFLASH Controller)
28.5.3

Read cycles - buffer miss

On an incoming AHB read request, a buffer lookup and access checks are performed during
the AHB address phase. In the event of a buffer miss the AHB address and attributes are
registered and the flash access is initiated the cycle following the AHB address phase (the
first AHB data phase cycle). If globally enabled, the calibration remap evaluation is also
performed during the first AHB data phase cycle. If the access is to be remapped, the
appropriate access is routed to the destination memory during the second AHB data phase
cycle.
If the flash access was the direct result of an AHB transaction, the corresponding page
buffer is marked as most-recently-used as it is being loaded. If the flash access was the
result of a speculative prefetch to the next sequential line, it is first loaded into the least-
recently-used buffer. The status of this buffer is not changed to most-recently-used until a
subsequent buffer hit occurs as a result of an AHB read request.
28.5.4 Read cycles – buffer hit
Single cycle read responses to the AHB are possible with the flash memory controller when
the requested read access was previously loaded into one of the page buffers. In these
"buffer hit" cases, read data is returned to the AHB data phase with a zero wait-state
response.
28.5.5 Error termination
The flash memory controller may invoke a system bus error termination in the following
scenarios:
• Attempted access by an AHB master whose corresponding Read Access Control or
Write Access Control settings do not allow the access, thus causing a protection
violation. See
more detail. In this case the flash memory controller does not initiate a flash array
access.
•
Attempted instruction fetch by an AHB master to the BAF flash region when the
PFCR3[BAF_DISABLE] field in Platform Flash Configuration Register 3 (PFCR3) is
set. The assertion of PFCR3[BAF_DISABLE] indicates that code stored in the BAF
region should not be executed. See
Register 3 (PFCR3)
initiate a flash array access.
•
Attempted access by an AHB master to a flash region, where the corresponding
censorship control is asserted.The flash returns an error response on an attempted
flash access (See
28.5.6 Flash error response operation
The flash array may signal an error response to terminate a requested access due to
improper sequencing during program/erase operations. When an error response is
received, the flash memory controller does not update or validate a page read buffer. An
error response may be signaled on read operations. For more information on the specifics
related to signaling of flash errors, including flash ECC events and read-while-write events,
refer to the flash array documentation.
580/2058
Section 28.4.1.3, Platform Flash Access Protection Register (PFAPR)
for more detail. In this case, the flash memory controller does not
Section 28.5.6, Flash error response
DocID027809 Rev 4
Section 28.4.1.2, Platform Flash Configuration
operation).
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