Table 1096. Rwd Byte Lane Mapping - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Nexus 3 Module
Table 1095. RWD data placement for transfers(Continued)
Transfer Size
and byte offset
Doubleword
first RWD pass (low order data)
second RWD pass (high order data)
Table Notes:
"X" indicates byte lanes with valid data
"—" indicates byte lanes that will contain unused data.
Table 1096
buses.
Transfer Size
and byte offset
Byte @000
Byte @001
Byte @010
Byte @011
Byte @100
Byte @101
Byte @110
Byte @111
Half @000
Half @010
Half @100
Half @110
Word @000
Word @100
Doubleword @000
first RWD pass
second RWD pass
Table Notes:
"—" indicates byte lanes that will contain unused data.
1942/2058
RWA(2:0)
0 0 0
shows the mapping of RWD bytes to byte lanes of the AHB read and write data

Table 1096. RWD byte lane mapping

RWA(2:0)
31:24
0 0 0 —
0 0 1 —
0 1 0 —
0 1 1 —
1 0 0 —
1 0 1 —
1 1 0 —
1 1 1 —
0 0 0 —
0 1 0 —
1 0 0 —
1 1 0 —
0 0 0 AHB[31:24]
1 0 0 AHB[63:56]
0 0 0
AHB[31:24]
AHB[63:56]
DocID027809 Rev 4
RWCS[SZ]
31:24
0 1 1 X
X
RWD
23:16
—
—
—
—
—
—
—
—
— AHB[15:8]
— AHB[31:24]
— AHB[47:40]
— AHB[63:56]
AHB[23:16] AHB[15:8]
AHB[55:48] AHB[47:40]
AHB[23:16] AHB[15:8]
AHB[55:48] AHB[47:40]
RM0400
RWD
23:16 15:8
X X
X X
15:8 7:0
— AHB[7:0]
— AHB[15:8]
— AHB[23:16]
— AHB[31:24]
— AHB[39:32]
— AHB[47:40]
— AHB[55:48]
— AHB[63:56]
AHB[7:0]
AHB[23:16]
AHB[39:32]
AHB[55:48]
AHB[7:0]
AHB[39:32]
AHB[7:0]
AHB[39:32]
7:0
X
X