Table 943. Dbcr5 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
.
0 1 2 3 4 5 6
1. Reset by processor reset p_reset_b if EDBCR0
EDBRAC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by
EDBRAC0 will be reset by p_reset_b.
Table 943
Bit Name
Instruction Address Compare 5 User/Supervisor Mode
00 IAC5 debug events not affected by MSR
0:1 IAC5US
01 Reserved
10 IAC5 debug events can only occur if MSR
11 IAC5 debug events can only occur if MSR
Instruction Address Compare 5 Effective/Real Mode
00 IAC5 debug events are based on effective address
2:3 IAC5ER
01 Unimplemented (Book E real address compare), no match can occur
10 IAC5 debug events are based on effective address and can only occur if MSR
11 IAC5 debug events are based on effective address and can only occur if MSR
Instruction Address Compare 6 User/Supervisor Mode
00 IAC6 debug events not affected by MSR
4:5 IAC6US
01 Reserved
10 IAC6 debug events can only occur if MSR
11 IAC6 debug events can only occur if MSR
Instruction Address Compare 6 Effective/Real Mode
00 IAC6 debug events are based on effective address
6:7 IAC6ER
01 Unimplemented (Book E real address compare), no match can occur
10 IAC6 debug events are based on effective address and can only occur if MSR
11 IAC6 debug events are based on effective address and can only occur if MSR
Instruction Address Compare 5/6 Mode
00 Exact address compare. IAC5 debug events can only occur if the address of the instruction
01 Address bit match. IAC5 debug events can occur only if the address of the instruction fetch,
8:9 IAC56M
10 Inclusive address range compare. IAC5 debug events can occur only if the address of the
11 Exclusive address range compare. IAC5 debug events can occur only if the address of the
10:15 — Reserved
1668/2058
0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 564; Read/Write; Reset
Figure 992. DBCR5 register
EDM
provides bit definitions for Debug Control Register 5.

Table 943. DBCR5 field descriptions

fetch is equal to the value specified in IAC5. IAC6 debug events can only occur if the address
of the instruction fetch is equal to the value specified in IAC6.
ANDed with the contents of IAC6 are equal to the contents of IAC5, also ANDed with the
contents of IAC6. IAC6 debug events do not occur. IAC5US and IAC5ER settings are used.
instruction fetch is greater than or equal to the value specified in IAC5 and less than the value
specified in IAC6. IAC6 debug events do not occur. IAC5US and IAC5ER settings are used.
instruction fetch is less than the value specified in IAC5 or is greater than or equal to the value
specified in IAC6. IAC6 debug events do not occur. IAC5US and IAC5ER settings are used.
(1)
=0, as well as unconditionally by m_por. If EDBCR0
Description
PR
=0 (Supervisor mode)
PR
=1. (User mode)
PR
PR
=0 (Supervisor mode)
PR
=1. (User mode)
PR
DocID027809 Rev 4
- 0x0
RM0400
0
=1,
EDM
=0
IS
=1
IS
=0
IS
=1
IS