Initialization/Application Information - STMicroelectronics SPC572L series Reference Manual

Interrupt Controller (INTC)
clock
interrupt request to processor
hardware vector enable
interrupt vector
interrupt acknowledge
read INTC_IACKRn
write INTC_EOIRn
INTVEC in INTC_IACKRn
PRI in INTC_CPRn
peripheral interrupt request 100
18.7

Initialization/application information

18.7.1 Initialization flow
After exiting reset, all of the PRIn and PRC_SELn fields in INTC_PSRn are zero, and PRI in
the INTC_CPRn registers is 63. These reset values will prevent the INTC from asserting the
interrupt request to the processors. The enable or mask bits in the peripherals are reset
such that the peripheral interrupt requests are negated. An initialization sequence for
allowing the peripheral and software-settable interrupt requests to cause an interrupt
request to the processor is:
•
Interrupt_request_initialization:
–
–
–
–
–
–
372/2058
Figure 115. Timing diagram for hardware vector mode handshaking
0
0
0
Configure HVENn in INTC_BCR.
Configure VTBAn in INTC_IACKRn.
Raise the PRIn fields and set the PRC_SELn fields to the desired processor in
INTC_PSRn.
Set the enable bits or clear the mask bits for the peripheral interrupt requests.
Lower PRI in INTC_CPRn to zero.
Enable processor(s) recognition of interrupts.
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