Tion - STMicroelectronics SPC572L series Reference Manual

RM0400
Figure 219. MC_CGM System Clock Ramp-Up Timing (k = 6 example)
f
f
targ
16MHz
1
24.4.1.3 System Clock Disable
During the TEST mode, the system clock can be disabled by the MC_ME.
24.4.1.4 System Clock Dividers
The MC_CGM generates the following derived clocks from the system clock:
• core clock - controlled by the CGM_SC_DC0 register
•
AIPS clock - controlled by the CGM_SC_DC1 register
• AIPS clock - controlled by the CGM_SC_DC2 register
24.4.1.4.1 System Clock Divider Synchronization
The system clock dividers are synchronized to each other such that the rising edges of the lower
frequency clocks are aligned with those of the higher frequency clocks. This, however, imposes
limitations on the division factors which can be used. In order for the synchronization to work properly,
each division factor must be selected such that its value is an integer multiple of each division factor that
has a lower value.
Table 271. MC_CGM Example System Clock Dividision Values Compatible with Divider
Divider
0
1
2
CGM_PCS_SDUR
f ÷ PCS_DIVSn[DIVS]
targ
2
Example 1. Correct System Clock Divider Configuration
Synchronization
Division Factor
1
2
6
DocID027809 Rev 4
Clock Generation Module (MC_CGM)
3 4
busy
CGM_SC_DC0[DIV] = 0
CGM_SC_DC1[DIV] = 1
CGM_SC_DC2[DIV] = 5
≤ a × f
targ
steps
6
5
Register Value
533/2058
541