Data Conversion Step - STMicroelectronics SPC572L series Reference Manual

Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface
1. Enable the SDADC by asserting MCR[EN].
2. Configure MCR to select the required mode, polarity, common mode voltage, input
gain, and decimation rate.
3. Enable high-pass filter if required.
4. Select the required analog channel for data conversion. It is possible to select the bias
for each channel for AC coupling applications.
5. Configure OSD delay according to SDADC startup time or latency from reset exit.
6. Generate a reset event by writing 0x5AF0 to RESET_KEY of RKR. Otherwise, if data
conversion need to be triggered by a hardware event, assert MCR[TRIGEN].
7. DFFF interrupt or DMA request will be generated after the data FIFO has reached
threshold to indicate that data can be transferred.
The following sequence needs to be followed when external modulator mode of SDADC is
selected for data conversions.
1. Disable the SDADC internal modulator by deasserting MCR[EN].
2. Configure MCR to select the external modulator mode.
3. Select the required external pins EMDATA/EMCLK in the system integration logic
(SIUL) of the device.
4. Configure OSD delay according to external modulator startup time or latency from reset
exit.
5. Generate a reset event by writing 0x5AF0 to RESET_KEY of RKR.
6. DFFF interrupt or DMA request will be generated after the data FIFO has reached
threshold to indicate that data can be transferred.
35.8.1

Data conversion step

To acquire a data from SDADC, the following sequence is required:
1. Enable the SDADC by asserting MCR[EN].
2. Configure MCR to select the required mode, polarity, common mode voltage, input
gain, and decimation rate.
3. Enable high-pass filter is required.
4. Select the required analog channel for data conversion. It is possible to select the bias
for each channel for AC coupling applications.
5. Configure OSD delay according to SDADC required startup time or latency from reset
exit.
6. Generate a reset event writing 0x5AF0 in RESET_KEY field of RKR register.
7. Wait till FIFO empty flag DFEF of SFR register is clear.
8. Read data by CDATA of CDR register.
Repeat steps from 6 to 8 for new acquisitions.
Note: The time elapsed between reset event and Read data by CDATA field of CDR register are:
• Reset event <- -> Data Valid flag(CDVS) = Output settling Time delay (Refer to the
t and t
settling
settling delay values.)
• Data Valid flag <- -> Data FIFO is not empty = 0.5*CLK_Out + 3*CLK_In
• Data FIFO is not empty <- -> read Data (safety point) = 2*CLK_In
754/2058
parameters in the device datasheet for the minimum allowed output
LATENCY
DocID027809 Rev 4
RM0400