RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
V
REFH_ADC
TCCAPR7[ICSEL_TCH3]
Bias
Generator
2/3
20K
1/3
TCCAPR7[ICSEL_TCH1]
V
TCCAPR7[ICSEL_TCH2]
REFL_ADC
TCCAPR7[ICSEL_TCH0]
Note:
1. Test channels are mapped to internal analog channels via the SARADCB_TCCAPRx registers.
Figure 324. SARADC block diagram
SoC Input
Switch Network
V
DD_HV_ADC_TSENS
Ω
bias current
V
SS_HV_ADC
_TSENS
DocID027809 Rev 4
V
REFH_ADC
SAR ADC
switch control
Precharge
ctrl
ADC
V
REFL_ADC
Digital
Interface
757/2058
803
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