Table 58. Protected Cmuiop Registers - STMicroelectronics SPC572L series Reference Manual

RM0400
Register
MCSR 612
MCSR 624
MCSR 628
MCSR 638-639
MCSR 643
MCSR 656-687
MCSR 758
MCSR 759
MCSR 936-967
SIUL2_GPDO0–511
SIUL2_PGPDO0–31
SIUL2_MPGPDO0–31
1. See the module memory map in the SIUL2 chapter for address offset.
6.7.12.2 Clock Monitor Unit (CMUIOP) protected registers
Table 58
Register
CMU_CSR
CMU_HFREFR_A
CMU_LFREFR_A
CMU_MDR
6.7.12.3 Power Manament Controller Digital Interface (PMC_dig)
Table 59
Register
REE_VD3
RES_VD3
REE_VD4
RES_VD4
REE_VD7
Table 57. Protected SIUL2 registers(Continued)
Register size (bits)
32
32
32
32
32
32
32
32
32
8
16
32
lists the registers that can be protected for the CMU_IOP.

Table 58. Protected CMUIOP registers

Register size (bits)
32
32
32
32
lists the registers that can be protected for the power management controller.
Table 59. Protected PMC_dig registers
Register size (bits)
32
32
32
32
32
DocID027809 Rev 4
Offset from module
base address
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
0x1300
0x1700
0x1780
Offset from module
base address
0x0
0x0008
0x000C
0x0018
Offset from module
base address
0x0034
0x0038
0x0044
0x0048
0x0074
Device configuration
Protected size (bits)
32
32
32
32
32
32 (×22)
32
32
32 (×32)
8 (×512)
16 (×32)
32 (×32)
Protected size (bits)
8 (byte 0)
32
32
32
Protected size (bits)
32
32
32
32
32
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