Port Configuration Register (Pcr) — Reference Only - STMicroelectronics SPC572L series Reference Manual

RM0400
Bits
CSC[7:4]
CSC[3:0]
66.4.2 Port Configuration Register (PCR) — reference only
The Port Configuration Register (PCR) controls the basic port functions for all Nexus
modules in a multi-Nexus environment. This includes clock control and auxiliary port width.
All bits in this register are writable only once after system reset.
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
Output Port Mode Control (SoC Level)
31 OPC 0 Reduced Port Mode configuration (min# nex_mdo[n:0] pins defined by SOC)
1 Full Port Mode configuration (max# nex_mdo[n:0] pins defined by SOC)
30 — Reserved for future functionality
MCKO Clock Enable (SoC Level)
29 MCK_EN 0 nex_mcko is disabled
1 nex_mcko is enabled
MCKO Clock Divide Ratio (see note below) (SoC Level)
000 nex_mcko is 1x processor clock freq.
001 nex_mcko is 1/2x processor clock freq.
010 Reserved (default to 1/2x processor clock freq.)
28:26 MCK_DIV 011 nex_mcko is 1/4x processor clock freq.
100 Reserved (default to 1/2x processor clock freq.)
101 Reserved (default to 1/2x processor clock freq.)
110 Reserved (default to 1/2x processor clock freq.)
111 nex_mcko is 1/8x processor clock freq.
25:0 — Reserved for future functionality
Note: The CSC and PCR Registers exist in a separate module at the SoC level in a multi-Nexus
environment. If the core Nexus 3 module is the only Nexus module, these registers are not
implemented and the Nexus 3 defined Development Control Register 1 (DC1) is used to
control the SoC-level Nexus port functionality.
Table 1078. CSC field descriptions
Reserved for future Nexus Clients (read as 0)
Client Select Control
0xx Nexus client (SoC level)
Nexus Reg# PCR_INDEX; Read/Write; Reset: 0x0
Figure 1131. Port Configuration Register (PCR)
Table 1079. PCR field descriptions
DocID027809 Rev 4
e200z215An3 Nexus 3 Module
Description
0
9 8
Description
7 6 5 4 3 2 1
1921/2058
0
1982