Introduction; Spc572Lx Microcontroller; Target Applications; Overall Architecture - STMicroelectronics SPC572L series Reference Manual

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Introduction

2.1

SPC572Lx microcontroller

The SPC572Lx microcontroller is a new member in a family of devices building on the
legacy of the superseded SPC56xx family while introducing new features coupled with
higher throughput to provide substantial reduction of cost per feature and significant power
and performance improvement (MIPS per mW). There is one e200z215An3 processor core
on the SPC572Lx device.
2.1.1

Target applications

This SPC57xx family of MCUs is targeted at automotive powertrain controller applications
for gasoline and diesel engines, chassis control applications, transmission control
applications, steering and braking applications, as well as low-end hybrid applications and
two-wheelers.
The SPC572Lx device is specifically designed for 2-wheeler applications, predominantly
motorcycles.
Many of these applications are considered to be functionally safe and are designed to be
ISO26262 compliant. SPC572Lx implements the necessary architecture features to target
ASIL-A integrity level.
2.1.2

Overall architecture

The shell, illustrated in
The architecture is based on an 80 MHz crossbar switch with master and slave ports. The
master ports connected are the two CPU ports (32-bit load/store and 32-bit instruction) and
a 32-bit 40 MHz concentrator port. A DMA unit, an LFAST interface and an Ethernet
controller are connected on the concentrator. As slave ports are connected the flash
memory controller, the SRAM controller and a Peripheral Bridge (PBRIDGE) to connect the
peripheral cluster.
From a software perspective, every bus master (CPU, DMA, SIPI, and Ethernet) sees every
memory and peripheral (all RAM modules, flash memory, and peripherals) in a consistent
flat memory map.
2.1.3

Core features

The SPC572Lx CPU comprises a single 32-bit 80 MHz e200z215An3 core including a
Nexus 3 module.
The CPU employs Power Architecture with enhancements that improve the architecture's fit
in embedded applications. The Power Architecture VLE instruction set supports code size
footprint reduction by encoding a mix of 16-bit and 32-bit instructions.
2.1.4

Memory hierarchy

The first level of memory is system RAM and flash memory. These are connected via an
80 MHz, 32-bit wide crossbar. The second level of memory system is the I/O subsystem. All
the I/O peripherals are connected together via an 80 MHz 32-bit wide crossbar switch, while
Figure 2, incorporates the core, the platform and the I/O subsystem.
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Introduction
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