Figure 116. Interrupt Request Block Diagram - STMicroelectronics SPC572L series Reference Manual

Interrupt Controller (INTC)
wrteei 1# enable external interrupts to the Processor
18.7.5.2.1.1 Interrupt request to processor
Referencing
INT_SOURCES
Assuming that there are no IRQn deasserted (no pending interrupt requests to processor n),
if one of the external interrupt sources (INT_SOURCES) has a priority higher than the
INTC_CPRn, then interrupt request to the processor (IRQn) is asserted. It will stay asserted
until one of the following conditions is true:
•
Interrupt acknowledge (IACK) is asserted
• If the EEn bit has been cleared by the wrteei instruction (see
re-evaluated when processor n writes to the INTC_CPRn while processor n ignores
IRQn
This provides a safe way to guarantee that no interrupts will be recognized by processor n
while updating the INTC_CPRn.
18.7.5.2.2 Raised priority preserved
Before the instruction after the GetResource system service executes, all pending
transactions have completed. These pending transactions can include an ISR for a
peripheral or software-settable interrupt request whose priority was equal to or lower than
the raised priority. The shared coherent data block now can be accessed coherently.
Figure 117
The example is for software vector mode. Except for the method of retrieving the vector and
acknowledging the interrupt request to the processor, hardware vector mode is identical.
378/2058
Figure 106, the interrupt request logic to the processor is shown in

Figure 116. Interrupt request block diagram

>
writeCPRn
IACKn
EEn
shows the timing diagram for this scenario, and
DocID027809 Rev 4
Interrupt
request
block
Figure
Table 163
RM0400
Figure 116.
IRQn
116), IRQn will be
explains the events.