Register Memory Maps And Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
The TestFlash block can be enabled by the BIU.When the Test space is enabled, all the
operations are mapped to the Test block.The TestFlash supports RWW and is grouped with
the Code flash in partition 0.
Erase of the TestFlash block is always locked in User mode.
Programming of any section of the TestFlash block is subject to similar restrictions as the
array in terms of how ECC is calculated. Only one program is allowed per 64-bit ECC
segment.
The TestFlash block contains two different user sections: UTEST (8 KB) and BAF (8 KB).
The UTEST Nonvolatile Memory section is OTP and erase is not allowed. User mode
programming of the UTEST section is enabled only when MCR[PEAS] is high. The UTEST
section is divided into a Flexible area where content is managed at SoC level, and a
Reserved area where addresses are pre-allocated for storing certain content. The UTEST
section may be locked and unlocked against programming via LOCK0[TSLOCK] in
conjunction with the relative sideband (SoC specific). For locking purposes, UTEST is
treated as a stand alone block even though it resides in the TestFlash block. UTEST access
(both Read and Modify) is disabled in Test mode once the Test Mode Disable Seal
password is written. As UTEST is part of the TestFlash physical block, it is also protected.
The UTEST section is also set as OPP once the Test Mode Disable Seal password is
written, thus programming is only allowed on virgin 64-bit locations.
The other area of the TestFlash block is BAF and may be used for defined functions
(possibly to store boot code, other configuration words or factory process codes). This
nonvolatile memory area is OTP and cannot be erased once programmed.
Although the BAF (like UTEST) is part of the TestFlash block, OPP functionality is managed
through sideband (SoC specific). Program protection is also managed through sideband
(SoC specific), in conjunction with LOCK0[LOWLOCK]. For locking and OPP purposes,
BAF is treated as a standalone block.
When the UTEST section (via the entire TestFlash block) is protected via Test Mode Disable
Seal, the BAF is also protected from any high voltage operation which may alter the content.
Access to BAF is read only for FPEC in the event that the test interface is open (Failure
Analysis scenario).
29.3

Register memory maps and descriptions

In this section some nonvolatile registers are described as well as the usual volatile
registers. Note that such entities are not Flip-Flops, but TestFlash block locations with a
specific purpose.
During the Flash Initialization phase, the FPEC reads these nonvolatile registers and
updates their corresponding volatile registers. When the FPEC detects ECC double errors
in these special locations, it behaves in the following way:
•
In case of failing system locations (configurations, redundancy, EmbAlgo firmware), the
initialization phase is interrupted and a Fatal Error is flagged.
•
In case of failing user locations (protections, censorship, BIU, etc.), the volatile
registers are filled with '1's and the Flash Initialization ends setting MCR[PEG] to low.
In this section, the following abbreviations are used:
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