Table 353. Sar Adc0 Register Definitions - STMicroelectronics SPC572L series Reference Manual

RM0400
34.2.2.10.2 SAR ADC0 register definitions
Name
SARADC0_MCR
SARADC0_MSR
SARADC0_ISR
SARADC0_ICIPR0
SARADC0_IMR

Table 353. SAR ADC0 register definitions

0 1 2 3
16 17 18 19
R 0
W
R 0 0 0 0
W
R 0 0 0 0
W
R CHADDR
W
R 0 0 0 0
W
R 0 0 0 0
W
R 0 0 0 0
W
R 0 0 0 0
W
R 0 0 0 0
W
R 0 0 0 0
W
DocID027809 Rev 4
Analog-to-digital converter (ADC) configuration
27 5 6 7 8
20 21 22 23 24
JTRGSEL
0 0 0
0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0
w1 w1
c c
0 0 0 0 0
0 0 0 0 0
9 10 11 12 13
25 26 27 28 29
0
0 0 0
0 0 0 0
0 0 0 0 ADCSTATUS
0 0 0 0 0
0 0 0
w1 w1
c c
0 0 0 0 0
w1 w1 w1 w1 w1
c c c c c
0 0 0 0 0
0 0 0
14 15
30 31
0 0
0
0 0
0 0
w1 w1
c c
0 0
w1 w1
c c
0 0
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