Dspi Push Fifo Register In Slave Mode (Dspi_Pushr_Slave) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Clear Transfer Counter.
Clears the SPI_TCNT field in the Transfer Count register.
5
The SPI_TCNT field is cleared before the DSPI starts transmitting the current SPI frame. Hence
CTCNT the current SPI frame causes this counter to increment by 1.
0 Do not clear the TCR[SPI_TCNT] field.
1 Clear the TCR[SPI_TCNT] field.
Parity Enable or Mask t
PE: This bit enables parity bit transmission and parity reception check for the SPI frame.
MASC: The current frame has the "after SCK" delay masked if this bit is asserted. See
Section 46.5.6.6: Fast Continuous Selection Format
6
This bit is used as Mask t
PE_MASC
0 PE: No parity bit included/checked.
MASC: t
1 PE: Parity bit is transmitted instead of the last data bit in the frame; parity is checked for the
received frame.
MASC: t
Parity Polarity or Mask t
PP: controls the polarity of the parity bit transmitted and checked.
MCSC: The next frame has the "PCS to SCK" delay masked if this bit is asserted. See
Section 46.5.6.6: Fast Continuous Selection Format
This bit is used as Mask t
7
0 PP: Even Parity: the number of 1 bits in the transmitted frame is even. The SR[SPEF] bit is set
PP_MCSC
if the number of 1 bits is odd in the received frame.
MCSC: t
1 PP: Odd Parity: the number of 1 bits in the transmitted frame is odd. The SR[SPEF] bit is set if
the number of 1 bits is even in the received frame.
MCSC: t
Select which PCS signals are to be asserted for the transfer.
8–15
Refer to the chip configuration chapter for the number of PCS signals used in this MCU.
PCS[7:0]
0 Negate the PCS[x] signal.
1 Assert the PCS[x] signal.
16–31 Transmit Data
TXDATA Holds SPI data to be transferred according to the associated SPI command
46.3.8

DSPI PUSH FIFO Register In Slave Mode (DSPI_PUSHR_SLAVE)

PUSHR provides the means to write to the TX FIFO.
Data written to this register is transferred to:
• The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.
In master mode, the register provides 16-bit command to the CMD FIFO and 16-bit data to
the TX FIFO.
In slave mode, CMD FIFO is unused and the 16-bit Command field of PUSHR is reserved.
In Slave mode, up to 32-bit SPI frames may be queued for transmission/reception by
enabling MCR[XSPI] mode.
Table 619. DSPI_PUSHR field descriptions(Continued)
delay in the current frame
ASC
in the Fast Continuous PCS mode when MCR[FCPCS] is set.
ASC
delay is not masked and the current frame has the after SCK delay.
ASC
delay is masked in the current frame.
ASC
delay in the next frame
CSC
in the Fast Continuous PCS mode when MCR[FCPCS] is set.
CSC
delay is not masked and the next frame has the PCS to SCK delay.
CSC
delay is masked in the next frame.
CSC
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