Interrupt Controller (Intc); Introduction; Block Diagram - STMicroelectronics SPC572L series Reference Manual

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Interrupt Controller (INTC)

18.1

Introduction

The INTC:
•
Provides priority-based preemptive scheduling of interrupt requests
•
Schedules interrupt requests (IRQs) from software and internal peripherals to one or
more processors (PRCs)
•
Provides interrupt prioritization and preemption, interrupt masking, interrupt priority
elevation, and protocol support
This scheduling scheme is suitable for statically scheduled hard real-time systems.
The INTC is targeted to work with a Power Architecture processor and is capable of
processing high-demand interrupt sources where the Interrupt Service Routines (ISRs) nest
to multiple levels, but it also can be used with other processors and applications.
For high-priority interrupt requests in these target applications, it is necessary to minimize
the interval between the assertion of the interrupt request from the peripheral and the point
at which the processor is performing useful work to service the interrupt request. The INTC
supports this goal by providing a unique vector for each interrupt request source. It also
provides 64 priorities so that lower priority ISRs do not delay the execution of higher priority
ISRs. Since each individual application will have different priorities for each source of
interrupt request, the priority of each interrupt request is configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the Priority Ceiling Protocol for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the resource are unable to preempt each other.
Multiple processors can assert interrupt requests to each other through software-settable
interrupt requests. These same software-settable interrupt requests can also be used to
separate the work involved in servicing an interrupt request into two parts, a high-priority
portion and a low-priority portion. The high-priority portion is initiated by a peripheral
interrupt request, but then the ISR can assert a software-settable interrupt request to finish
the servicing in a lower priority ISR. Therefore these software-settable interrupt requests
can be used instead of having the peripheral ISR schedule a task through the RTOS.
18.2

Block diagram

Figure 106
actual number of processors is described in the chip-specific INTC information. The
structure of the INTC remains the same for each implemented processor.
shows the block diagram of an INTC with four processors (PRC0...PRC3). The
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