Table 109. Embedded Floating-Point Data Interrupt—Register Settings - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 108. System Reset Interrupt—register settings(Continued)
Register
ESR Cleared
DEAR Undefined
Vector [p_rstbase[0:29]] || 2'b00
12.6.5.11 Embedded Floating-point Data Interrupt (offset 0xA0)
The Embedded Floating-point Data interrupt is taken if no higher priority exception exists
and an EFPU Floating-point Data exception is generated. When a Floating-point Data
exception occurs, the processor suppresses execution of the instruction causing the
exception.
Table 109
Table 109. Embedded Floating-point Data Interrupt—register settings
Register
SRR0 Set to the effective address of the excepting EFPU instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE —
EE 0
PR 0
ESR SPV, VLEMI. All other bits cleared.
MCSR Unchanged
DEAR Unchanged
Vector IVPR || 0xA0
0:23
12.6.5.12 Embedded Floating-point Round Interrupt (offset 0xB0)
The Embedded Floating-point Round interrupt is taken when an EFPU floating-point
instruction generates an inexact result and inexact exceptions are enabled.
Table 110
Table 110. Embedded Floating-point Round Interrupt—register settings
Register
SRR0 Set to the effective address of the instruction following the excepting EFPU instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE —
EE 0
PR 0
lists register settings when an EFPU Floating-point Data interrupt is taken.
FP
ME
FE0
DE
lists register settings when an EFPU Floating-point Round interrupt is taken.
FP
ME
FE0
DE
DocID027809 Rev 4
Setting description
Setting description
0
—
0
—
Setting description
0
—
0
—
Core e200z215An3 description
FE1 0
IS 0
DS 0
PMM 0
RI —
FE1 0
IS 0
DS 0
PMM 0
RI —
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