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Enhanced Direct Memory Access (eDMA)
19.3.25
TCD Destination Address (DMA_TCDn_DADDR)
See TCD Destination Address register figure and DMA_TCDn_DADDR field descriptions
table as follows.
FC0A_0000h base + 1010h offset + (32d × n), where n = 0d to
Address:
63d
0
1
R
W
(1)
Reset
x
x
16
17
R
W
Reset
x
x
Figure 143. TCD Destination Address (DMA_TCDn_DADDR)
1. x = Undefined at reset.
Field
0–31
Destination address
DADDR
Memory address pointing to the destination data.
19.3.26
TCD Current Minor Loop Link, Major Loop Count (Channel Linking
Enabled) (DMA_TCDn_CITER_ELINKYES)
See TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) register
figure and DMA_TCDn_CITER_ELINKYES field descriptions table as follows.
Address: FC0A_0000h base + 1014h offset + (32d × n), where n = 0d to 63d
0
1
R
E
LINK
W
(1)
Reset
x
x
Figure 144. TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
1. x = Undefined at reset.
422/2058
2
3
4
5
x
x
x
x
18
19
20
21
x
x
x
x
Table 188. DMA_TCDn_DADDR field descriptions
2
3
4
5
LINKCH
x
x
x
x
(DMA_TCDn_CITER_ELINKYES)
DocID027809 Rev 4
6
7
8
9
DADDR
x
x
x
x
22
23
24
25
DADDR
x
x
x
x
Description
6
7
8
9
x
x
x
x
Access: User read/write
10
11
12
13
x
x
x
x
26
27
28
29
x
x
x
x
Access: User read/write
10
11
12
13
CITER
x
x
x
x
RM0400
14
15
x
x
30
31
x
x
14
15
x
x
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