STMicroelectronics SPC572L series Reference Manual page 962

GTM101 Integration (GTMINT) Module
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ECC encoder / decoder for each of 8 RAM interfaces
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m. Note that by enabling two MCS cores at the same time for data trace can exceed the capacity of the NAR
Client interface throughput thus information can be lost.
962/2058
– IEEE 1149.1 (JTAG) Test Access Port (TAP)
Support for optional Multi-JTAG TAP Linking Module (TLM)
4 pins (TDI, TDO, TMS, and TCK)
Reset input TRST driven by either the Nexus Port Controller or an external
pin
GTM Development Support
– Read/Write registers in debug mode from JTAG port
– Ability to enter debug mode at reset negation or during normal execution
– Breakpoint and Watchpoint Configuration
– Data Trace via Data Write Messaging (DWM) and Data Read Messaging
(DRM). This allows the development tool to trace reads and writes to selected
RAM address ranges
Two data trace windows for each MCS core with programmable address
ranges and access attributes are provided. Data trace windowing reduces the
requirement on the Aurora port bandwidth by constraining the number of
trace locations.
Fetch trace capability controlled by two programmable Watchpoints.
Private messages are used to indicate special MCS core cases not covered
by public messages. Up to two
time.
– Watchpoint Messaging (WPM)
Trigger Control
– The GTMDI provides selection of trigger signals that will generate debug
actions at system level such as Halt GTM itself or cores in the same device.
– Trace enable signals are provided to control the start/stop of trace messages
for each one of the GTM Nexus message sources, such as TIM, TOM, ATOM,
etc.
GTMDI Clock operation
– The module is able to operate in any frequency ratio considering GTMDI and
JTAG frequency. The GTMDI should operate in the same clock source as the
GTM IP module.
Parity calculation using the whole word and the target memory address value.
Detection and correction of single error on the read data value
Detection of single bit error on address field but no need for correction
Double error detection on data or address field without error correction.
ECC report generation for each RAM containing:
– Address of the error in the register map (see
register definition)
– Non-correctable error indication (not correctable data + address ECC
detected errors)
DocID027809 Rev 4
(m)
MCS cores can be debugged at the same
Section 43.2, Memory map and
RM0400