STMicroelectronics SPC572L series Reference Manual page 584

Flash memory controller (PFLASH Controller)
Buddy Device (Extended) Overlay RAM
Note the trace data from the Nexus Aurora Router (PD-NAR) can only be routed to the on-
chip overlay RAM; there is a different connection path in the Buddy Device from the BD-
NAR into the extended overlay RAM.
The system RAM connection from the calibration remap logic is implemented via a private
32-bit connection to the platform's RAM controller. Since the calibration access is defined to
have the same access time as a normal flash array access, remapped references to the
system RAM are treated as the highest priority request by the platform's RAM controller.
Accesses to the flash arrays always use the logical, non-remapped system address.
Calibration data store references to the system RAM, on-chip or buddy device (extended)
overlay RAM always use the physical, non-remapped system address. Conversely,
calibration data load references can be accessed using a translated physical address or, if
provided by the requesting master, the physical, non-remapped system
address.Doubleword-sized data store references to the on-chip overlay RAM are supported.
Byte-, halfword-, word- and doubleword-sized store references to the on-chip calibration
RAM or the buddy device (extended) overlay RAM are supported. The read data interface of
system RAM is 32-bits wide and the on-chip overlay RAM interfaces are each 64-bits wide,
whereas the flash read data interface is 128-bits wide. As a result, a remapped calibration
access initiates a four-beat burst sequence to mimic the throughput of a single flash access.
There is a direct relationship between the operating frequency range and the required
number of wait states to correctly sample flash read data. By contrast, a remapped
calibration access has a fixed 4-beat latency. The access time of each individual beat
depends on the overlay target (system RAM, on-chip overlay RAM, or buddy device).
Therefore, PFCR1[RWSC] must be programmed to a value such that the overall flash
access latency sufficiently covers the required access time to complete a 4-beat burst
sequence from the slowest available overlay target at the specified device operating
frequency to guarantee the latency for an initial, random calibration access accurately
mimics the flash access time. Expressed mathematically:
Notice the overall latency as perceived by the requesting master on a random, initial flash
access incurs two additional cycles beyond the intrinsic flash access time. The overall
latency on a remapped overlay access incurs one additional cycle beyond the burst access
time. These cycles accounts for pipleine stalls incurred by the flash controller state machine.
Calibration data that is available in the flash controller's mini-cache is returned with single-
cycle latency
There are memory-mapped calibration remap (region) descriptor (CRDn) registers which
define the required address translation. Each calibration remap descriptor includes the
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Table 292. Calibration data memory base addresses(Continued)
Calibration memory
On-chip Overlay RAM
( RWSC 1 ) ≥ (
+
where
RWSC = ceiling
DocID027809 Rev 4
Base address
0x0D00_----
0x0C{0,1}-_----
( OverlayRAMTranferLatency 4
IntrinsicFlashAccessTime

------------------------------------------------------------------------------------------------ -

OperatingFrequencyClockPeriod
Possible access sources
P0, P1, PD-NAR
P0, P1
× ) 1 )
+


RM0400