Table 682. Low Speed 4 Phase Selection - Sampling Procedure - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
For High speed 4 Phase selection, See
Phase Select algorithm Phase 1 is mapped to Phase0, Phase 3 is mapped to Phase 2,
Phase 5 is mapped to Phase 4, Phase 7 is mapped to Phase 6 so it simplifies the algorithm
and allows the algorithm to be the same independent of 4 or 8 Phases in high speed.
Samplers
For low speed 4 Phase selection, See
four Samplers (0,1,2,3) of the low 4 phase speed selection algorithm are the same as the
four samplers required for the high 8 phase speed. Therefore the same architecture can be
used for both high speed and low speed with the other four data paths disabled for low
speed.
47.7.2.2.4 Sampler block and phase enable and disable
There are 8 data sampler paths in total inside the auto-correlation block, each data sampler
has 3 sampling registers with the possibility of each register being clocked by a different
phase (in example, Sampler 5 for high speed can have Phases 5, 2 and 0). Therefore after
the correct data sampler has been selected for either high or low speed, the block can turn
off all the sampler paths except for one, therefore 3 out of 24 registers will remain enabled
while the others are disabled, as shown in
After correlation and the correct data sampler has been selected all the other data samplers
whose initial phase does not match the select phase are disabled. The selected sampler will
then keep the required phases needed enabled, this can be max 3 phases (e.g Sampler 5
has Phases 5, 2, 0) or min 1 phase (in example, Sampler 0 has all Phase 0 content).
The end result is that the Rx Controller can disable the required number of unused sampler
registers and disable any unnecessary phases from the Clocking Module by de-asserting
the respective phase enables.

Table 682. Low speed 4 phase selection - sampling procedure

Initial
Sample Phase
0 Phase 0
1 Phase 1
2 Phase 2
3 Phase 3
4 Disabled
5 Disabled
6 Disabled
7 Disabled
DocID027809 Rev 4
Table 681, Samplers 1, 3, 5, 7 are disabled. In the
Intermediate Sample
Phase
Phase 0
Phase 0
Phase 0
Phase 0
Disabled
Disabled
Disabled
Disabled
Table 682, Samplers 4, 5, 6, 7 are disabled.The first
Figure 670.
Final
Sample Phase
Phase 0
Phase 0
Phase 0
Phase 0
Disabled
Disabled
Disabled
Disabled
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