External Signal Description - STMicroelectronics SPC572L series Reference Manual

Reset Generation Module (MC_RGM)
reset in the case where the chip is configured to execute a self-test on power-on,
'destructive', and external resets. 'Functional' resets are:
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When a reset is triggered, the MC_RGM state machine is activated and proceeds through
the different phases (i.e., PHASEn states). Each phase is associated with a particular chip
reset being provided to the system. A phase is completed when all corresponding phase
completion gates from either the system or internal to the MC_RGM are acknowledged. The
chip reset associated with the phase is then released, and the state machine proceeds to
the next phase up to entering the IDLE phase. During this entire process, the MC_ME state
machine is held in RESET mode. Only at the end of the reset sequence, when the IDLE
phase is reached, does the MC_ME enter the DRUN mode.
Alternatively, it is possible for software to configure some reset source events to be
converted from a reset to either a SAFE mode request issued to the MC_ME or to an
interrupt issued to the core (see <Cross Refs>Section 51.3.1.2, 'Destructive' Event Reset
Disable (RGM_DERD) register and <Cross Refs>Section 51.3.1.3, 'Destructive' Event
Alternate Request (RGM_DEAR) register for 'destructive' resets and <Cross
Refs>Section 51.3.1.6, 'Functional' Event Reset Disable (RGM_FERD) register and <Cross
Refs>Section 51.3.1.7, 'Functional' Event Alternate Request Register (RGM_FEAR) for
'functional' resets).
51.2

External signal description

The MC_RGM interfaces to the bidirectional reset pin ESR0.
1510/2058
ESR0 external reset
ESR1 external reset
software 'functional' reset
System Watchdog reset
Core Watchdog reset
JTAG 'functional' reset request
core debug reset
oscillator failure
system frequency out of range
PLL0 lock failure
temperature sensor 'functional' reset
voltage out of range 'functional' reset
Flash fatal error reset
DocID027809 Rev 4
RM0400