Table 553. Rx Fifo 0 Configuration Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
44.3.5.2.28 Rx Buffer Configuration Register (RXBC)
Address: 0x00AC
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R
W
Reset 0 0 0

Table 553. Rx FIFO 0 Configuration register field descriptions

Field
0:15 Reserved
Rx Buffer Start Address
16:29
Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).
RBSA
Also used to reference debug messages A,B,C.
30:31 Reserved
44.3.5.2.29 Rx FIFO 1 Configuration Register (RXF1C)
Address: 0x00B0
0 1 2
R 0
W
Reset 0 0 0
16 17 18
R
W
Reset 0 0 0
1. These are protected write (P) bits which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0
[INIT] of CCCR register are set to "1".
3 4 5 6
0 0 0 0
0 0 0 0
19 20 21 22
RBSA
0 0 0 0
Figure 498. Rx FIFO 0 Configuration register
3 4 5 6
(1)
F1WM
0 0 0 0
19 20 21 22
F1SA
0 0 0 0
Figure 499. Rx FIFO 0 Configuration register
DocID027809 Rev 4
7 8 9 10
0 0 0 0
0 0 0 0
23 24 25 26
0 0 0 0
Description
7 8 9 10
0
0 0 0 0
23 24 25 26
1
0 0 0 0
CAN Subsystem
Access: RP
11 12 13 14
0 0 0 0
0 0 0 0
27 28 29 30
0
0 0 0 0
Access: RP
11 12 13 14
F1S
0 0 0 0
27 28 29 30
0
0 0 0 0
1035/2058
15
0
0
31
0
0
15
0
31
0
0
1091