Table 557. Tx Buffer Configuration Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

CAN Subsystem
44.3.5.2.32 Tx Buffer Configuration Register (TXBC)
Address: 0x00C0
0 1 2
R 0
W
Reset 0 0 0
16 17 18
R
W
Reset 0 0 0
1. These are protected write (P) bits which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0
[INIT] of CCCR register are set to "1".

Table 557. Tx Buffer Configuration register field descriptions

Field
0 Reserved
Tx FIFO/Queue Mode
1
0 Tx FIFO operation
TQFM
1 Tx Queue operation
Tx FIFO/Queue Size
2:7
0 No Tx FIFO/Queue
TQFS 1-32 Number of Tx Buffers used for Tx FIFO/Queue
>32 Values greater than 32 are interpreted as 32
8:9 Reserved
Number of Dedicated Transmit Buffers
10:15
0 No Dedicated Tx Buffers
NDTB 1-32 Number of Dedicated Tx Buffers
>32 Values greater than 32 are interpreted as 32
16:29 Tx Buffers Start Address
TBSA Start address of Tx Buffers section in Message RAM (32-bit word address, see
30:31 Reserved
Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.
1038/2058
3 4 5 6
(1)
TFQS
0 0 0 0
19 20 21 22
TBSA
0 0 0 0
Figure 502. Tx Buffer Configuration register
DocID027809 Rev 4
7 8 9 10
0 0
0 0 0 0
23 24 25 26
1
0 0 0 0
Description
RM0400
Access: RP
11 12 13 14
1
NDTB
0 0 0 0
27 28 29 30
0
0 0 0 0
Figure 514).
15
0
31
0
0