Table 389. Pdedr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
36.5.1.15 Power Down Exit Delay Register (PDEDR)
Offset 0x0C8
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Field
0–23
24–31
PDED
36.5.1.16 Internal Channel Data Registers 0–95 (ICDR0–ICDR95)
The conversion results for each channel is loaded into data registers. Each data register will
contain the conversion result, status information related to ADC mode, data valid and some
control information to select the required reference voltage, timing parameter selection for
each channel.
Offset 0x100–0x27C
0 1
R 0
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 344. Internal Channel Data Registers (ICDR0–ICDR95)
784/2058
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 343. Power Down Exit Delay Register (PDEDR)

Table 389. PDEDR field descriptions

Reserved
Write of any value has no effect; read value is always 0.
Power down exit delay duration.
Defines the delay between the power-down bit reset and the starting of conversion.
The power-down delay is calculated as [PDED
2 3 4 5
0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0
0 0 0 0
Description
6 7 8 9
0 0
0 0 0 0
22 23 24 25
CDATA[15:0]
0 0 0 0
Access: User Read/Write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
PDED
0 0 0 0
×
1/(SARADC clock frequency)].
Access: User Read/Write
10 11 12 13
0 0
0 0 0 0
26 27 28 29
0 0 0 0
14 15
0 0
0 0
30 31
0 0
14 15
0 0
30 31
0 0