Introduction - STMicroelectronics SPC572L series Reference Manual

Serial Interprocessor Interface (SIPI)
45 Serial Interprocessor Interface (SIPI)
45.1

Introduction

The Serial Interprocessor Interface (SIPI) is an application layer protocol that runs on top of
the LFAST module. It is used by the local device to access the shared memory of a remote
device. SIPI defines point-to-point full duplex communication between two devices, where
LFAST works as a physical medium of communication between both the devices.
45.1.1 Scalability
The SIPI protocol is designed to provide a sophisticated, high bandwidth, multimaster, multi-
channel memory interface between two devices using few interconnecting signals. But the
protocol is designed in such a way that a subset of the protocol can be implemented, where
die area is more important than features.
Main scalable features:
• Number of concurrent channels:
–
–
•
Full implementation has a node both as Initiator and Target of commands. Minimum
Implementation either Initiator or Target
•
Full Implementation includes a block transfer feature, but this feature is optional.
The rest of this section describes a full implementation of SIPI, which includes:
•
Advanced High-Performance Bus (AHB-Lite) master interface
• Direct Memory Access (DMA) interface
•
LFAST Tx/Rx (transmit/receive) interfaces along with Peripheral Bus Interface (IPS).
45.2 Overview
An instance of SIPI can act as initiator, or target or both. SIPI can access the shared
memory directly through its AHB master interface or through its DMA interface. DMA
interface is used when the node acts as an initiator while the AHB Master interface will be
used when the node acts as target. SIPI has four channels, with one channel (Channel 2)
having data streaming capability. Payload width for channel 0, 1 and 3 is 32 bits, and for
channel 2 data widths can be 32 bits, or 256 bits when streaming. Any of these channels
can be used for DMA access or bus interface access depending on the setting of the
SIPI_CCRn. CRC encoder calculates the CRC on the command frame. Then the SIPI
initiator appends the CRC to the end of the frame before transmission.
1092/2058
Full Implementation = 4
Minimum Implementation = 1
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