Flash Memory Controller (Pflash) Configuration - STMicroelectronics SPC572L series Reference Manual

RM0400
Topic
Embedded memories
System memory map
Platform Flash
Platform RAM Controller
Embedded flash memory
Decorated Storage Memory Controller
6.4.1

Flash memory controller (PFLASH) configuration

The flash controller provides flash configuration and control functions and manages the
interface between the flash memory array and the crossbar switch. The configuration and
control functions are accessed via control registers, which are read/write accessible only in
supervisor mode.
Three of the registers, PFCR1, PFCR2, and PFAPR, control the interaction of master
modules with the flash array by enabling/disabling prefetch or by controlling access to the
flash array on a per-master basis. Use of the fields in these registers requires knowledge of
the number assigned to each master. For example, the PFAPR[M2AP] field controls flash
array access by master 2, the PFAPR[M3AP] field controls flash array access by master 3,
and so on.
The master assignments are shown in
assignments used elsewhere in the chip, e.g., the SMPU.
Table 29. Reference links to related information
Chapter 28: Flash memory controller (PFLASH Controller)
Chapter 28: Flash memory controller (PFLASH Controller)
Chapter 30: Decorated Storage Memory Controller (DSMC)
Table 30. Flash controller bus master assignments
Bus master number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
DocID027809 Rev 4
Reference
Chapter 3: Embedded memories
Chapter 5: Memory map
Chapter 27: RAM controller (PRAM)
Table 30. Note that these are the same master
Device configuration
Bus master
Core
Reserved
Reserved
DMA
Ethernet
Reserved
Reserved
SIPI/LFAST
Core Debug
Reserved
Reserved
Reserved
Reserved
Reserved
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