Figure 64. Mscr I/O Pin And Ip Block Port Connectivity - STMicroelectronics SPC572L series Reference Manual

RM0400
independent of the others, except in the case of an LVDS configuration, where two MSCRs
must be configured together in this mode.
The MSCRs are divided into two sets:
•
I/O pin Multiplexed Signal Configuration Registers (SIUL2_MSCR_IO_0–
SIUL2_MSCR_IO_511)
•
Multiplexed Signal Configuration Registers for Multiplexed Input Selection
(SIUL2_MSCR_MUX_512–SIUL2_MSCR_MUX_1023)
The signal data flow from IP blocks on the device to and from the I/O pins, and from IP block
to IP block is given in
Port (output)
IP Block 0
Port (output)
.
.
.
Port (output)
IP Block n
Port (input)
.
.
.
Port (output)
IP Block z
Port (input)
13.2.2.11.1 I/O Pin Multiplexed Signal Configuration Registers (SIUL2_MSCR_IO_0–
SIUL2_MSCR_IO_511)
The I/O pin MSCR definition is given in
on the associated I/O pin. The I/O MSCRs control the drive strength, output drive circuit, pull
up/down, input buffer enable, input hysteresis, input level selection, safe-mode operation,
and analog input enable of the associated I/O pin.
Note that when an I/O pin is configured as a single-ended input, the input buffer must be
enabled for the pin using the MSCR[IBE] bit. This enables the input to all input destinations
connected to the pin, including the GPIO input. In this way, the GPIO can be read at any
time, regardless of the pin function. For IP blocks that have multiple input sources, the input
source is selected in the multiplexed input selection MSCRs, and the associated I/O pin
MSCR for the selected input must have the MSCR[IBE] bit enabled.
Figure 64.

Figure 64. MSCR I/O pin and IP block port connectivity

.
.
.
Input Muxing MSCR
.
.
.
DocID027809 Rev 4
System Integration Unit Lite2 (SIUL2)
I/O Pin MSCR
Figure 65. These registers select the output function
Output
buffer
I/O Pin 0
Input
buffer
.
.
.
I/O Pin n
Input
buffer
297/2058
308