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Clocking
Note: All dividers shown in the diagram are integer dividers
with a range of 1, 2, 3,...., n.
FCD are fractional clock dividers.
All clock dividers are 50% duty cycle.
8 – 40 MHz
Ext. oscillator
(XOSC)
ext. clock
AUX Clock 3
Selector
XOSC
16 MHz RC
oscillator
(IRCOSC)
IRCOSC
LFAST_CLK
PBRIDGEA_CLK
CAN_CLK
cu_hclk
(M_CAN)
CCCU
cu_pclk
CCCU_CLK
See Note 1
TXCLK_REF_CLK
(Ethernet)
FEC_REF_CLK
1
See
Figure 165
for Ethernet clocking details
462/2058
Figure 161. Clock generation
PHI1
PLL0
PHI
PLL0:PHI
CMU_0
4 phases
320 MHz
0
÷ 1...64
XOSC
0
÷ 1...16
DocID027809 Rev 4
XOSC
IRCOSC
XOSC
IRCOSC
XOSC
IRCOSC
XOSC
IRCOSC
XOSC
XOSC
CORE_CLK (Core)
0
÷ 1...64
XBAR_CLK (XBAR)
1
÷ 1...64
PBRIDGEA_CLK
0
peripherals (PER_CLK)
÷ 1...16
1
SDADC (SD_CLK)
÷ 1...128
2
÷ 1...128
SARADC (SAR_CLK)
0
FCD
1
÷ 1...16
0
÷ 1...512
0
÷ 1...128
0
÷ 1...64
RM0400
50% duty cycle
50% duty cycle
DSPI_4
(DSPI_CLK0)
DSPI_0
(DSPI_CLK1)
LIN_CLK
SYSCLK1
RF_REF
DRCLK
SENT (SENT_CLK)
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