Initialization/Application Information - STMicroelectronics SPC572L series Reference Manual

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68.5

Initialization/application information

68.5.1 Reset
The reset state of each individual bit is shown within the Register Description section (see
Section 68.2.1, Register
DCF records stored in the UTEST Flash memory block.
68.5.2 Modifying Life Cycle (maturing the device)
The life cycle can be modified by an external life cycle management device like SSCM. It is
no longer controlled through the PASS module.
68.5.3 Setting lock bits in a password group
There is no restriction on setting and clearing lock registers in the UTEST Flash, apart from
the available space for DCF records. It is possible to set and clear them multiple times.
Table 1139. Flash Memory Read Protection Truth Table
INPUTS
Debug Interface
Enable
Don't Care
Don't Care
Blocked
Enabled
Don't Care
Don't Care
descriptions). However, many bits receive their values based on
Table 1140. CS/ADDR Values for Lock Registers
Register
Lock0
Lock1
Lock2
Lock3
DocID027809 Rev 4
Password and Device Security Module (PASS)
Read Protected
Lock3[RLx]
RL[0] (UTEST)
Don't Care Readable
Don't Care Readable
Don't Care Readable
Locked (1) Read Blocked
Unlocked (0) Readable
Don't Care Readable
Locked (1) Readable
Unlocked (0) Readable
PW Group 0
PW Group 1
OUTPUTS
Read Protected
RL[2:1] (Other
Regions)
Readable
Readable
Readable
Read Blocked
Readable
Readable
Read Blocked
Readable
DCF CS/ADDR
(1)
0xxxxx _0100
1
0xxxxx _0104
1
0xxxxx _0108
1
0xxxxx _010C
2009/2058
2011