Table 1012. Jtagm_Dor3 Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset 0x14
0 1 2 3
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The JTAGM_DOR3 register is described in
Field
0–27
Lower word of data for TDI, bits 27–0. Writable by software only when DTM = 1. TDI_LOW[0] is
shifted out first
TDI_LOW
28–30 Reserved
31 Send bit. When this bit is set, data is sent to the DCI. It is a self-clearing bit and is always read as 0.
SEND Writable by software only when DTM = 1
62.4.1.7 Data input register 0 (JTAGM_DIR0)
Figure 1060
Offset 0x1C
0 1 2 3
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The JTAGM_DIR0 register is described in
Field
0–31
Lower word of data received on TDO, bits 0–31
TDO_LOW
62.4.1.8 Data input register 1 (JTAGM_DIR1)
Figure 1061
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Figure 1059. JTAGM_DOR3 register

Table 1012. JTAGM_DOR3 register field descriptions

shows the format of the JTAGM_DIR0.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 1060. JTAGM_DIR0 register
Table 1013. JTAGM_DIR0 register field descriptions
shows the format of the JTAGM_DIR1.
DocID027809 Rev 4
TDI_LOW
Table 1012.
Description
TDO_LOW
Table 1013.
Description
JTAG Master (JTAGM)
Access: User read/write
31
0 0 0
0
Access: Read
1813/2058
1814