STMicroelectronics SPC572L series Reference Manual page 194

Reset and Boot
7.4.3.1 Assumptions
•
Boot Assist Flash bypass mode is not enabled (execute BAF code).
•
Application code for the Boot CPU is programmed into flash memory.
•
A valid boot header has been programmed into flash memory.
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The MC_RGM has passed control to the SSCM during the IDLE state.
7.4.3.2 Reset Generation Module has entered idle state (state 1 and 2)
Once the IDLE phase is signaled, the System Status and Control Module (started in
PHASE3) continues with the system boot-up sequence while the MC_RGM waits for new
events that trigger a reset sequence.
At this point:
• The data in the DCF record has been written to the appropriate registers.
•
All the trim values for the analog portions of the chip have been installed in their proper
locations.
7.4.3.3 Is a JTAG request pending? (state A)
The SSCM is now in charge of the boot-up sequence. It begins by determining whether a
JTAG request is pending. The JTAG test circuitry is for production test and used by software
development systems. The JTAG mode has no user functions and should never be used in
a user application. System designers must ensure that the external JTAG request pins
cannot inadvertently cause a JTAG test request.
7.4.3.4 Is the Boot Assist Flash bypass mode enabled? (state B)
The SSCM examines a status bit to determine whether the Boot Assist Flash bypass mode
is enabled. If this mode is enabled, any eventual code in the BAF is not executed. The BAF
bypass mode is enabled/disabled using a DCF record.
The DCF record supplied by the factory disables the bypass mode. This means that the
code in the Boot Assist Flash is always executed during a boot-up sequence.
The factory BAF code also runs the serial boot loader, setting up pins on the device to act as
a UART: receiving a file using a defined format and transferring the program portion of the
file to RAM. Once the program is installed, the SSCM begins core execution at the start
address specified in the file header.
7.4.3.5 Provide reset vectors to Core (state 21)
During PHASE3 of the Reset Generation Module's sequence, the start address for
execution of the BAF code is transferred to the MC_ME.
The SSCM releases reset to the core and turns on the core clock. The BAF code start
address is transferred to the core at this time under the control of the SSCM. Execution of
the Boot Assist Flash code begins.
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Boot Header_ID
Boot CPU selection
Boot CPU start address (address of first instruction in application code)
CPU reset vector
DocID027809 Rev 4
RM0400