Table 945. Dbcr7 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Bit Name
Instruction Address Compare 7 Extended Mask Control. IAC7XM allows for binary power of 2
address range compares for IAC7 without requiring the use of IAC8.
0000 No additional masking when DBCR5[IAC78M] = 00
24:27 IAC7XM
0001–1100
1101 – 1111 = Reserved
Instruction Address Compare 8 Extended Mask Control. IAC8XM allows for binary power of 2
address range compares for IAC8 without requiring the use of IAC7.
0000 No additional masking when DBCR5[IAC78M] = 00
28:31 IAC8XM
0001–1100
1101–1111
57.3.2.7 Debug Control Register 7 (DBCR7)
Debug Control Register 7 is used to enable and configure Data Address Compare 3 and 4
functionality. DBCR7 is shown in
0
0 1 2 3 4 5 6
1. DBCR7 is reset by processor reset p_reset_b if EDBCR0
EDBRAC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by
EDBRAC0 will be reset by p_reset_b.
Table 945
Bit Name
0:12 —
13 DAC3XMH
14 —
15 DAC4XMH
Table 944. DBCR6 field descriptions (Continued)
Exact Match Bit Mask. Number of low order bits masked in IAC7 when comparing
the storage address with the value in IAC7 for exact address compare
(DBCR5[IAC78M] = 00). Ranges up to 4 KB are supported.
Exact Match Bit Mask. Number of low order bits masked in IAC8 when comparing
the storage address with the value in IAC8 for exact address compare
(DBCR5[IAC78M] = 00). Ranges up to 4 KB are supported.
Reserved
0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 596; Read/Write; Reset
Figure 994. DBCR7 register
provides bit definitions for Debug Control Register 7.

Table 945. DBCR7 field descriptions

Reserved
Data Address Compare 3 Extended Mask Control High. DAC3XMH extends the range of
the DAC3XM field.
0 DAC3XM masks 0–15 low-order address bits
1 DAC3XM masks 16–31 low-order address bits
Reserved
Data Address Compare 4 Extended Mask Control High. DAC4XMH extends the range of
the DAC4XM field.
0 DAC4XM masks 0–15 low-order address bits
1 DAC4XM masks 16–31 low-order address bits
DocID027809 Rev 4
e200z215An3 Core Debug Support
Description
Figure 994.
0 DAC3XM
(1)
- 0x0
=0, as well as unconditionally by m_por. If EDBCR0
EDM
Description
DAC4XM DAC3CFG DAC4CFG
=1,
EDM
1671/2058
1719