Error Status Register (Dma_Es) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Enable debug
30
0 When in Debug mode the DMA continues to operate.
EDBG 1 When in Debug mode, the DMA stalls the start of a new channel. Executing channels are
allowed to complete. Channel execution resumes when the system or the EDBG bit is cleared.
31
This bit is reserved and always has the value zero.
Reserved
19.3.2

Error Status Register (DMA_ES)

The ES provides information concerning the last recorded channel error. Channel errors can
be caused by a configuration error (an illegal setting in the transfer-control descriptor or an
illegal priority register setting in Fixed Arbitration mode) or an error termination to a bus
master read or write cycle.
See <Cross Refs>Section 19.4.3, Error reporting and handling, for more details.
Address: FC0A_0000 + 0x0004
0 1
R VLD 0
W
Reset 0 0
16 17
R 0 CPE
W
Reset 0 0
Field
ERRL status bits
0
0 No ERR bits are set
VLD
1 At least one ERR bit is set indicating a valid error exists that has not been cleared
1–13
This read-only bitfield is reserved and always has the value zero.
Reserved
Uncorrectable ECC error
14
0No uncorrectable ECC error
UCE
1The last recorded error was an uncorrectable TCD RAM error
Transfer cancelled
15
0 No cancelled transfers
ECX
1 The last recorded entry was a cancelled transfer by the error cancel transfer input
16 This read-only bitfield is reserved and always has the value zero.
Reserved
Table 165. DMA_CR field descriptions(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
ERRCHN
0 0 0 0
Figure 120. Error Status Register (DMA_ES)
Table 166. DMA_ES field descriptions
DocID027809 Rev 4
Enhanced Direct Memory Access (eDMA)
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
SAE SOE DAE DOE NCE SGE SBE DBE
0 0 0 0
Description
Access: User read-only
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
14 15
UCE ECX
0 0
30 31
0 0
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