STMicroelectronics SPC572L series Reference Manual page 265

RM0400
Table 93. EFPU Status and Control Register field descriptions(Continued)
Bits Name
14
FOVFS
(46)
15
MODE
(47)
16
—
(48)
17
—
(49)
18
FG
(50)
19
FX
(51)
20
FINV
(52)
21
FDBZ
(53)
22
FUNF
(54)
23
FOVF
(55)
24
—
(56)
Embedded Floating-point Overflow Sticky Flag
The FOVFS bit is set to 1 when a floating-point instruction sets the FOVF bit to 1. The
FOVFS bit remains set until it is cleared by a mtspr instruction specifying the SPEFSCR.
Embedded Floating-point Operating Mode
This bit controls the operating mode of the EFPU.
e200z215An3 supports only mode 0.
Software should read the value of this bit after writing it to determine if the implementation
supports the selected mode. Implementations will return the value written if the selected
mode is a supported mode, otherwise the value read will indicate the hardware supported
mode.
0 Default hardware results operating mode
1 IEEE754 hardware results operating mode (not supported by Zen)
Reserved
Reserved
Embedded Floating-point Guard bit
FG is supplied for use by the Floating-point Round exception handler. FG is zeroed if a
Floating-point Data Exception occurs.
Embedded Floating-point Sticky bit
FX is supplied for use by the Floating-point Round exception handler.FX is zeroed if a
Floating-point Data Exception occurs.
Embedded Floating-point Invalid Operation / Input error
In mode 0, the FINV bit is set to 1 if the A or B operand of a floating-point instruction is
Infinity, NaN, or Denorm, or if the operation is a divide and the dividend and divisor are
both 0.
In mode 1, the FINV bit is set on an IEEE754 invalid operation (IEEE754-1985 sec7.1).
Embedded Floating-point Divide by Zero
The FDBZ bit is set to 1 when a floating-point divide instruction executed with divisor of 0,
and the l dividend is a finite nonzero number.
Embedded Floating-point Underflow
The FUNF bit is set to 1 when the execution of a floating-point instruction results in an
underflow.
Embedded Floating-point Overflow
The FOVF bit is set to 1 when the execution of a floating-point instruction results in an
overflow.
Reserved
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