STMicroelectronics SPEAr300 Reference Manual

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Introduction

This reference manual provides complete hardware information for application developers of

the SPEAr300 embedded MPU.

The SPEAr300 is a member of the SPEAr3xx family (includes SPEAr300, SPEAr310 and

SPEAr320).

SPEAr3xx devices all feature ARM926EJ-S core running up to 333 MHz, an external DDR2

Memory Interface, a common set of powerful on-chip peripherals. Each member of the

SPEAr3xx family has a specific set of IPs implemented in its Reconfigurable Array

Subsystem (RAS). In the SPEAr300, the following IPs are implemented in the RAS.

●

FSMC NAND/NOR Flash interface

●

SDIO controller

●

Color LCD controller (CLCD)

●

Telecom IP with TDM interface, camera interface, I2S, 18 GPIOs (G8 and G10), DAC,

SPI_I2C chip selects.

●

Keyboard controller

For the pin out, ordering information, mechanical, electrical and timing characteristics,

please refer to the SPEAr300 Datasheet.

For information on the ARM926EJ-S core, please refer to the ARM926EJ-S Technical

Reference Manual.

April 2011

Doc ID 018672 Rev 1

RM0082

Reference manual

SPEAr300

1/844

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Summary of Contents for STMicroelectronics SPEAr300

Page 1 This reference manual provides complete hardware information for application developers of the SPEAr300 embedded MPU. The SPEAr300 is a member of the SPEAr3xx family (includes SPEAr300, SPEAr310 and SPEAr320). SPEAr3xx devices all feature ARM926EJ-S core running up to 333 MHz, an external DDR2 Memory Interface, a common set of powerful on-chip peripherals.
Page 2: Table Of Contents
Contents RM0082 Contents Acronyms ..........52 Preface .
Page 3 RM0082 Contents 5.3.3 Boot pins ..........70 5.3.4 GPIOs .
Page 4 Contents RM0082 8.6.8 VICINTENCLEAR register ........97 8.6.9 VICSOFTINT register .
Page 5 10.13.1 Register overview ........149 10.13.2 MPMC base address In SPEAr300 ......149 10.13.3 Register map .
Page 6 Contents RM0082 10.13.12 MEM7_CTL register ........160 10.13.13 MEM8_CTL register .
Page 7 RM0082 Contents 10.13.49 MEM46_CTL register ........176 10.13.50 MEM47_CTL register .
Page 8 Contents RM0082 11.2.1 Processor clock ......... . 203 11.2.2 DDR controller clock .
Page 9 RM0082 Contents 12.4.24 Special configuration parameters ......243 12.4.25 Powerdown_CFG_CTR register ......243 12.4.26 COMPSSTL_1V8_CFG/DDR_2V5_COMPENSATION register .
Page 10 Contents RM0082 13.4.8 DMA interface ......... . . 273 13.4.9 Synchronizing registers and logic .
Page 11 RM0082 Contents BS_System controller ........286 14.1 Overview .
Page 12 Contents RM0082 15.6.1 Latencies ..........304 15.7 How to boot from external memory .
Page 13 RM0082 Contents 17.2.5 TIMER_STATUS_INT_ACK register ......322 17.2.6 TIMER_COMPARE register ....... . . 323 17.2.7 TIMER_COUNT register .
Page 14 Contents RM0082 19.4.1 AHB slave interface ........335 19.4.2 AHB master interfaces .
Page 15 RM0082 Contents 20.2.3 CONTROL register ........352 20.2.4 STATUS register .
Page 16 Contents RM0082 21.6.16 Byte bucket control register (HIF_NCR) ..... . . 376 21.6.17 Instruction dispatcher registers (C3_IDn) ..... . 377 21.6.18 Channel registers (C3_CHn) .
Page 17 RM0082 Contents 21.10.3 Feedback registers (AES_FEEDBACK) ......392 21.10.4 Counter registers (AES_COUNTER) ......393 21.10.5 Control and status register (AES_CONTROL_STATUS) .
Page 18 Contents RM0082 22.3.3 OHCI host controller ........413 22.4 EHCI host controller blocks .
Page 19 RM0082 Contents 22.6.22 Register description of OHCI ....... 440 22.6.23 Operation registers ........440 22.6.24 The control and status partition .
Page 20 Contents RM0082 23.3.5 Endpoint FIFO controller (Transmit FIFO controller) ....467 23.3.6 Control and status registers ....... . . 468 23.3.7 AHB slave-only interface .
Page 21 RM0082 Contents 23.8.12 Endpoint status register ........499 23.8.13 Endpoint buffer size and received packet frame number register .
Page 22 Contents RM0082 24.7.11 Missed frame and buffer overflow counter register (Register8, DMA) . 533 24.7.12 Current host transmit descriptor register (Register18, DMA) ..533 24.7.13 Current host receive descriptor register (Register19, DMA) ..534 24.7.14 Current host transmit buffer address register (Register20, DMA) .
Page 23 RM0082 Contents 25.3.6 FIFO buffers ..........558 25.3.7 Internal memories .
Page 24 Contents RM0082 26.5.1 External pin connection ........578 26.5.2 Register map .
Page 25 RM0082 Contents 27.4.11 UARTMIS Register ........604 27.4.12 UARTICR register .
Page 26 Contents RM0082 28.6.19 IC_CLR_INTR register(0x040) ......634 28.6.20 Interrupt clearing registers(0x044 - 0x068) ..... 635 28.6.21 IC_ENABLE register(0x06C) .
Page 27 RM0082 Contents 30.1.9 ATA_PABX_I2S MODE (ATA PABX with I2S) ....655 30.1.10 CAMl_LCDw MODE (8 bit CAMERA without LCD) ....655 30.1.11 CAMu_LCD MODE (14 bit CAMERA with LCD) .
Page 28 Contents RM0082 RS_SDIO controller ........678 32.1 Overview .
Page 29 RM0082 Contents 32.7.27 MAXCURR2 register ........728 32.7.28 ACMD12FEERSTS register .
Page 30 Contents RM0082 33.6.7 LCD timing 3 register ........754 33.6.8 LCDUPBASE and LCPLPBASE registers .
Page 31 RM0082 Contents 34.4.13 IT bus ..........782 34.5 Programmer’s model .
Page 32 Contents RM0082 35.3 Programming model ........811 35.3.1 External signals .
Page 33 RM0082 Contents 38.4.4 X-Loader and U-boot Header ....... 829 38.4.5 X-Loader and U-boot authentication .
Page 34 List of Tables RM0082 List of Tables Table 1. Acronyms ............. . 52 Table 2.
Page 35 RM0082 List of Tables Table 49. SoC interconnection matrix scheme ......... 103 Table 50.
Page 36 List of Tables RM0082 Table 101. MEM23_CTL register bit assignments ........167 Table 102.
Page 37 RM0082 List of Tables Table 153. Memory controller parameters ..........185 Table 154.
Page 38 List of Tables RM0082 Table 205. RAS_GPP_EXT_IN register bit assignments ........269 Table 206.
Page 39 RM0082 List of Tables Table 257. PRESCALER configuration ..........322 Table 258.
Page 40 List of Tables RM0082 Table 309. REG2MC register bit assignments ......... . 356 Table 310.
Page 41 RM0082 List of Tables Table 361. CONFIGFLAG register bit assignments ........434 Table 362.
Page 42 List of Tables RM0082 Table 413. Endpoint register bit assignments......... . . 503 Table 414.
Page 43 RM0082 List of Tables Table 465. MMC transmit interrupt register bit assignments ....... 550 Table 466.
Page 44 List of Tables RM0082 Table 518. UART control and status register summary ........594 Table 519.
Page 45 RM0082 List of Tables Table 570. IC_DMA_CR register bit assignments ........640 Table 571.
Page 46 List of Tables RM0082 Table 622. Determination of transfer type ..........700 Table 623.
Page 47 RM0082 List of Tables Table 674. Color palette register ........... . 749 Table 675.
Page 48 List of Tables RM0082 Table 728. External signals ............811 Table 729.
Page 49 SPEAr300 - Core architecture overview ........
Page 50 List of figures RM0082 Figure 49. UDC-AHB subsystem memory map ......... 490 Figure 50.
Page 51 RM0082 List of figures Figure 101. DAC used with TDM at 8 kHz ..........780 Figure 102.
Page 52: Acronyms
Acronyms RM0082 Acronyms The below table contains acronyms and abbreviations that are used in this document. Table 1. Acronyms Terms Expansion Analog to Digital Convertor Advanced Encryption Standard Analog Front End Arithmetic Logic Unit ASIC Application Specific Integrated Circuit Application Subsystem AMBA Advanced Micro controller Bus Architecture AMBA High speed Bus...
Page 53 RM0082 Acronyms Table 1. Acronyms (continued) Terms Expansion LIFO Last-In-First-Out Low speed Subsystem Least Significant Bit Media Access Control Micro-Controller Unit MD-5 Message Digest 5 Memory Management Unit Most Significant Bit OHCI Open Host Controller Interface Physical layer Random Access Memory Reconfigurable Array Subsystem Radio Frequency Reserved for Future Use...
Page 54: Preface
Preface RM0082 Preface Terms & conditions The following terms are used hereafter in this document. ● Reserved - All reserved or unused bits of registers must be written as zero, and ignored on read unless otherwise stated in the relevant text. Conventions 2.2.1 Numbering...
Page 55: Reference Documentation
RM0082 Reference documentation Reference documentation ARM926EJ-S – Technical reference manual AMBA specification (ARM IHI 0011A), rev. 2.0 USB 2.0 specification OHCI specification EHCI specification ISO/IEC 10918-1 (International Organization for Standardization) Doc ID 018672 Rev 1 55/844...
Page 56: Product Overview
Product overview RM0082 Product overview Device overview An outline picture of the main SPEAr300 functional interfaces is shown in Figure Figure 1. SPEAr300 top view USB Device USB2 Host DDR2/DDR Low UART Power GPIO IrDA TDM/BUS SPEAr300 Serial Flash Interface...
Page 57: Main Features
RM0082 Product overview 4.1.1 Main features The following main functionalities are implemented in SPEAr300 embedded MPU device: ● ARM926EJ-S core @333 MHz, 16+16 KB-I/D cache, configurable TCM-I/D size, MMU, TLB, JTAG and ETM trace module (multiplexed interfaces). ● Dynamic power saving features.
Page 58: Architecture Properties
Product overview RM0082 Architecture properties ● Power save features: – Operating frequency SW programmable. – Clock gating functionality. – Low frequency operating mode. – Automatic power saving controlled from application activity demands. ● Architecture easily extensible. ● External memory bandwidth of each master tuneable to meet the target performances of different applications.
Page 59: System Architecture Overview
System architecture overview 4.3.1 Core architecture The internal architecture is based on several-shared subsystem logics interconnected through a multilayer interconnection matrix as shown in the Figure Figure 2. SPEAr300 - Core architecture overview SPEAr300 Debug JTAG/ETM9 subsystem ARM926EJS Timer 16+16KB-I/D Cache...
Page 60: Cpu Subsystem
Product overview RM0082 throughput. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round-robin arbitration mechanism. CPU subsystem ● ARM926EJ-S running at 333 MHz with: – – 16 Kbyte of instruction cache –...
Page 61: Basic Subsystem
RM0082 Product overview Basic subsystem ● Eight high performance DMA channels with two AHB interfaces to parallelize the activity when two channels are working at the same time. ● 32 Kbyte of ROM. ● Serial Flash interface capable of working up to 50 Mbps. ●...
Page 62: Application Subsystem
DES/3DES with ECB, CBC modes. ● MD5, SHA-1, SHA256 with HMAC. 4.11 Reconfigurable logic array subsystem The SPEAr300 also includes certain specific functions: ● 8/16 bits parallel Flash interface allowing connection of NOR or NAND Flash and asynchronous SRAM. ●...
Page 63: Clock And Reset System
RM0082 Product overview 4.12 Clock and reset system ● The system clocks are generated by three PLLs: – Two of them are fully programmable (the first one generates the clock for CPU and AMBA system; instead the second one generates the clock for the RAS block and for the DDR Memory interface.
Page 64: Pin Description
Pin description RM0082 Pin description The following tables describe the pinout of the SPEAr300 listed by functional block. List of abbreviations: PU = Pull Up PD = Pull Down Required external components Ω ● DDR_COMP_1V8: place an external 121 k resister between ball P4 and ball R4 Ω...
Page 65: Table 4. Power Supply Pin Description
RM0082 Pin description Table 4. Power supply pin description (continued) Group Signal name Ball Value HOST0_VDDbc 2.5 V USB HOST0 PHY HOST0_VDDb3 3.3 V HOST0_VDDbs 1.2 V HOST1_VDDbc 2.5 V USB HOST1 PHY HOST1_VDDb3 3.3 V HOST1_VDDbs 1.2 V DEVICE_VDDbc 2.5 V USB DEVICE PHY DEVICE_VDDb3...
Page 66: Table 6. Serial Memory Interface (Smi) Pin Description
Pin description RM0082 Table 6. Serial memory interface (SMI) pin description Group Signal name Ball Direction Function Pin type Serial Flash input TTL Input Buffer SMI_DATAIN Input data 3.3 V tolerant, PU Serial Flash SMI_DATAOUT Output output data TTL output buffer SMI_CLK Serial Flash clock 3.3 V capable 4...
Page 67: Table 8. Adc Pin Description
RM0082 Pin description Table 8. ADC pin description Group Signal name Ball Direction Function Pin type AIN_0 AIN_1 AIN_2 AIN_3 ADC analog input channel AIN_4 Analog buffer Input 2.5 V tolerant AIN_5 AIN_6 AIN_7 ADC_VREFN ADC negative voltage reference ADC_VREFP ADC positive voltage reference Doc ID 018672 Rev 1 67/844...
Page 68: Table 9. Ddr Pin Description
Pin description RM0082 Table 9. DDR pin description Group Signal name Ball Direction Function Pin type DDR_ADD_0 DDR_ADD_1 DDR_ADD_2 DDR_ADD_3 DDR_ADD_4 DDR_ADD_5 DDR_ADD_6 DDR_ADD_7 Output Address Line DDR_ADD_8 DDR_ADD_9 DDR_ADD_10 SSTL_2/SSTL_18 DDR_ADD_11 DDR_ADD_12 DDR_ADD_13 DDR_ADD_14 DDR_BA_0 DDR_BA_1 Output Bank select DDR_BA_2 DDR_RAS Output...
Page 69 RM0082 Pin description Table 9. DDR pin description (continued) Group Signal name Ball Direction Function Pin type DDR_CS_0 Output Chip Select DDR_CS_1 DDR_ODT_0 On-Die Termination DDR_ODT_1 Enable lines DDR_DATA_0 DDR_DATA_1 SSTL_2/SSTL_18 DDR_DATA_2 DDR_DATA_3 Data Lines (Lower byte) DDR_DATA_4 DDR_DATA_5 DDR_DATA_6 DDR_DATA_7 DDR_DQS_0 Lower Data...
Page 70: Shared I/O Pins (Pl_Gpios)
Output buffer: TTL 3.3 V capable up to 10 mA – Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD) The PL_GPIOs can be configured in 13 different modes. This allows SPEAr300 to be tailored for use in various applications, see Section 30.1 5.3.1...
Page 71: Gpios
RM0082 Pin description Table 11. Booting pins B3-B0 Boot device 0000 USB Device 0001 ETH - MAC address in I2C 0010 ETH - MAC address in SPI 0011 Serial NOR 0100 Parallel NOR 8bit (FSMC) 0101 Parallel NOR 16bit (FSMC) 0110 Nand 8bit 0111...
Page 72: Figure 3. Multiplexing Scheme
Pin description RM0082 Figure 3. Multiplexing scheme Alternate functions RAS IP configuration mode 1 PL_GPIO RAS IP configuration mode 13 4 bits RAS Register 2 16 bits RAS Register 1 72/844 Doc ID 018672 Rev 1...
Page 73: Table 12. Available Peripherals In Each Configuration Mode
RM0082 Pin description Table 12. Available peripherals in each configuration mode GPIOs 16-bit NAND 16-bit 16-bit NAND 8-bit 8-bit NAND /NOR 8-bit 14-bit 14-bit 8-bit TDM interfacing using GPIOs In some configuration modes where less than 8 TDM devices are indicated in Table additional TDM devices can be supported by using GPIO pins.
Page 74: Table 13. Pl_Gpio Multiplexing Scheme
Table 13. PL_GPIO multiplexing scheme Alternate Configuration mode (enabled by RAS register 2) PL / function (enabled by number register 1) 97/H16 96/H15 COL0 COL0 COL0 COL0 COL0 COL0 COL0 COL0 95/H14 COL1 COL1 COL1 COL1 COL1 COL1 COL1 COL1 94/H13 COL2 COL2...
Page 75 Table 13. PL_GPIO multiplexing scheme (continued) Alternate Configuration mode (enabled by RAS register 2) PL / function (enabled by number register 1) 73/A17 CLD7 G8_7 (out) CLD7 CLD7 Reserved CLD7 Reserved CLD7 72/B16 CLD8 CLD8 CLD8 Reserved CLD8 Reserved CLD8 71/D14 CLD9 CLD9...
Page 76 Table 13. PL_GPIO multiplexing scheme (continued) Alternate Configuration mode (enabled by RAS register 2) PL / function (enabled by number register 1) 51/D10 CLLP G10_6 CLLP G10_6 CLLP G10_6 G10_6 G10_6 CLLP G10_6 CLLP 50/A12 TMR_CPTR4 CLLE G10_5 CLLE G10_5 CLLE G10_5 G10_5...
Page 77 Table 13. PL_GPIO multiplexing scheme (continued) Alternate Configuration mode (enabled by RAS register 2) PL / function (enabled by number register 1) 29/A7 BasGPIO1 SD_DAT2 SD_DAT2 SD_DAT2 SD_DAT2 SD_DAT2 SD_DAT2 SD_DAT2 SD_DAT2 SD_DAT2 SD_DAT2 SD_DAT2 28/A6 BasGPIO0 SD_SDAT3 SD_SDAT3 SD_SDAT3 SD_SDAT3 SD_SDAT3 SD_SDAT3 SD_SDAT3 SD_SDAT3 SD_SDAT3 SD_SDAT3 SD_SDAT3...
Page 78 Table 13. PL_GPIO multiplexing scheme (continued) Alternate Configuration mode (enabled by RAS register 2) PL / function (enabled by number register 1) 4/C1 I2C_SCL 3/D1 UART_RX 2/E4 UART_TX 1/E3 IrDA_RX 0/F3 IrDA_TX CCLK/ CCLK/TCL CCLK/ CCLK/ CCLK/ CK1/K17 PL_CLK1 TCLK* TCLK* TCLK* TCLK*...
Page 79: Pl_Gpio Pin Sharing For Debug Modes
RM0082 Pin description Notes/legend for Table GPIO (General purpose I/O): ● basGPIO: Base GPIOs in the basic subsystem (enabled as alternate functions) ● G10 and G8: GPIOs in the telecom subsystem ● GPIOx: GPIOs in the independent GPIO block in the RAS subsystem TDM_: DM interface signals SD_: SDIO interface IT pins: interrupts...
Page 80: Table 15. Ball Sharing During Debug
Pin description RM0082 Table 15. Ball sharing during debug Signal Case 1 - Board debug Case 2 - Static debug Case 3 - Full debug Test [0] Test [1] Test [2] Test [3] Test [4] nTRST nTRST_bscan nTRST_ARM nTRST_ARM TCK_bscan TCK_ARM TCK_ARM TSM_bscan...
Page 81 RM0082 Pin description Table 15. Ball sharing during debug (continued) Signal Case 1 - Board debug Case 2 - Static debug Case 3 - Full debug PL_GPIO [73] BSR Value Functional I/O ARM_TRACE_PKTB[7] PL_GPIO [72:0] Doc ID 018672 Rev 1 81/844...
Page 82: Memory Map
Memory map RM0082 Memory map Table 16. Main memory map Start address End address Notes 0x0000.0000 0x3FFF.FFFF DDR2 or Low Power DDR 0x4000.0000 0xBFFF.FFFF Table 22: Reconfigurable array subsystem 0xC000.0000 0xCFFF.FFFF Reserved 0xD000.0000 0xD7FF.FFFF Table 18: Low speed subsystem 0xD800.0000 0xDFFF.FFFF Table 21: Application subsystem 0xE000.0000...
Page 83 RM0082 Memory map Table 19. Basic subsystem Start address End address Peripheral Notes 0xF800.0000 0xFBFF.FFFF Serial Flash memory 0xFC00.0000 0xFC1F.FFFF Serial Flash controller 0xFC20.0000 0xFC3F.FFFF reserved 0xFC40.0000 0xFC5F.FFFF DMA controller 0xFC60.0000 0xFC7F.FFFF SDRAM controller 0xFC80.0000 0xFC87.FFFF Timer 1 0xFC88.0000 0xFC8F.FFFF Watch dog timer 0xFC90.0000 0xFC97.FFFF...
Page 84 Memory map RM0082 Table 22. Reconfigurable array subsystem Base Address Address Space 0x50000000 0x5000_0000 - 0x5FFF_FFFF TELECOM 0x60000000 0x6000_0000 - 0x6FFF_FFFF CLCD 0x70000000 0x7000_0000 - 0x7FFF_FFFF SDIO 0x80000000 0x8000_0000 - 0x98FF_FFFF FSMC 0x80000000 0x8000_0000 - 0x83FF_FFFF FSMC NAND on PCBank0 0x84000000 0x8400_0000 - 0x87FF_FFFF FSMC NAND on PCBank1...
Page 85: Cpu Subsystem_Arm926Ej-S
RM0082 CPU subsystem_ARM926EJ-S CPU subsystem_ARM926EJ-S Overview The ARM926EJ-S is a powerful processor, targeted for multi-tasking applications. Belonging to ARM9 general purposes family microprocessor, its main outstanding feature is its Memory management unit, which provides virtual memory features, making it also compliant with advanced operating system, like Linux.
Page 86: Functional Description
CPU subsystem_ARM926EJ-S RM0082 Functional description Figure 4. ARM926EJ-S block diagram External Coprocessor DRDATA IRDATA Interface DRWDATA CPUINST CPUOUT CPUIN interface Coprocessor DEXT interfac interface Write buffer Data DCACHE DROUTE Cache Interface Write back TAGRAM Write buffer WDATA RDATA Interface ARM9EJ-S FCSE unit INSTR...
Page 87: Caches And Write Buffer
RM0082 CPU subsystem_ARM926EJ-S The MMU TLB consists of two parts: ● The main TLB, which is a two-way, set-associative cache for page table information. It has 32 entries per way for a total of 64 entries. ● The lockdown TLB, which is an eight-entry fully-associative cache that contains locked TLB entries.
Page 88 CPU subsystem_ARM926EJ-S RM0082 The BIU contains separate masters for both instruction and data access, enabling multi- layer AHB and multi-AHB systems to be implemented, giving the benefit of increased overall bus bandwidth and a more flexible system architecture. To increase system performance, write buffers are used to prevent AHB writes stalling the ARM926EJ-S system.
Page 89: Cpu Subsystem_Vectored Interrupt Controller (Vic)
RM0082 CPU subsystem_Vectored interrupt controller (VIC) CPU subsystem_Vectored interrupt controller (VIC) Overview Acting as an interrupt controller, the VIC determines the source that is requesting service and where its interrupt service routine (ISR) is loaded, doing that in hardware. In particular, the VIC supplies the starting address, or vector address, of the ISR corresponding to the highest priority requesting interrupt source.
Page 90: Main Functions Description
CPU subsystem_Vectored interrupt controller (VIC) RM0082 Figure 5. VIC block diagram Non-vectored FIQ FIQSTATUS nVICFIQ interrupt logic [31:0] Non-vectored IRQ IRQSTATUS interrupt logic [31:0] Interrupt IRQ0 request Vector interrupt 0 VICINTSOURCE[31:0] VectAddr0 logic IRQ1 Vector interrupt 1 VectAddr1 IRQn vector VectAddrn address IRQ15...
Page 91: Non-Vectored Irq Interrupt Logic
If the interrupt is not currently being serviced, the highest priority request generates an IRQ interrupt. Note: External interrupt is not being used in SPEAr300. 8.3.6 Software interrupts The software can control the source interrupt lines to generate software interrupts (VICSOFTINT register, Section 8.6.9: VICSOFTINT...
Page 92: Interrupt Connection Table
CPU subsystem_Vectored interrupt controller (VIC) RM0082 Interrupt connection table Table 23. Interrupt sources Interrupt sources IRQ # Reserved Generic Interrupt #3 from RAS CPU Subsystem Timer 1_1 CPU Subsystem Timer 1_2 Basic Subsystem Timer 1_1 Basic Subsystem Timer 1_2 Basic Subsystem Timer 2_1 Basic Subsystem Timer 2_2 Basic Subsystem DMA (Direct Memory Access) Basic Subsystem SMI (Serial Memory Interface)
Page 93: How To Reduce Interrupt Latency
RM0082 CPU subsystem_Vectored interrupt controller (VIC) How to reduce interrupt latency The interrupt latency depends on the type of interrupt, see Table Table 24. Interrupt latency for different types of interrupts Worst case (cycles) Event IRQ (reduced latency) Interrupt synchronization Worst case interrupt disable period Entry to first instruction Nesting, assuming single-state AHB...
Page 94: Table 25. Vic Interrupt Control Registers Summary
CPU subsystem_Vectored interrupt controller (VIC) RM0082 Table 25. VIC interrupt control registers summary (continued) Name Offset Type Reset value Description VICRAWINTR 0x008 Raw interrupt status VICINTSELECT 0x00C 32’h0 Interrupt select VICINTENABLE 0x010 32’h0 Interrupt enable VICINTENCLEAR 0x014 Interrupt enable clear VICSOFTINT 0x018 32’h0...
Page 95: Register Description
RM0082 CPU subsystem_Vectored interrupt controller (VIC) Table 27. VIC interrupt vector control registers summary Name Offset Type Reset value Description VICVECTCNTL0 0x200 32’h0 VICVECTCNTL1 0x204 32’h0 VICVECTCNTL2 0x208 32’h0 VICVECTCNTL3 0x20C 32’h0 VICVECTCNTL4 0x210 32’h0 VICVECTCNTL5 0x214 32’h0 VICVECTCNTL6 0x218 32’h0 VICVECTCNTL7 0x21C...
Page 96: Vicfiqstatus Register
CPU subsystem_Vectored interrupt controller (VIC) RM0082 Table 29. VICIRQSTATUS register bit assignments Reset Name Description value Each bit is associated to an interrupt. [31:00] IRQStatus 32’h0 If a bit is set, it indicates that the relevant interrupt is active, and generates an interrupt to the processor. 8.6.4 VICFIQSTATUS register The VICFIQSTATUS is the RO register which provides the status of the interrupts after FIQ...
Page 97: Vicintenable Register
RM0082 CPU subsystem_Vectored interrupt controller (VIC) Table 32. VICINTSELECT register bit assignments Reset Name Description value Each bit is associated to an interrupt line. Each bit allows to select the type of interrupt for relevant interrupt requests, according to encoding: [31:00] IntSelect 32’h0...
Page 98: Vicsoftintclear Register
CPU subsystem_Vectored interrupt controller (VIC) RM0082 Table 35. VICSOFTINT register bit assignments Reset Name Description value Each bit is associated to a source interrupt. [31:00] SoftInt 32’h0 Setting a bit, a software interrupt for the specific source interrupt is generated before interrupt masking. 8.6.10 VICSOFTINTCLEAR register The VICSOFTINTCLEAR is a WO register which allows to clear bits in the VICSOFTINT...
Page 99: Vicdefvectaddr Register
RM0082 CPU subsystem_Vectored interrupt controller (VIC) Table 38. VICVECTADDR register bit assignments Reset Name Description value Reading from this register provides the address of the currently active ISR, indicating that the interrupt is being serviced. [31:00] Vector Addr 32’h0 Writing to this register indicates that the interrupt has been serviced and the interrupt is cleared.
Page 100: Vicperiphid0 Register
CPU subsystem_Vectored interrupt controller (VIC) RM0082 Table 40. Peripheral identification registers bit assignments Name Description This is the configuration option of the peripheral. the [31:24] Configuration configuration value is 0. This is the revision number of the peripheral. The revision [23:20] Revision number number starts from 0.
Page 101: Vicperiphid3 Register
RM0082 CPU subsystem_Vectored interrupt controller (VIC) Table 43. VICPERIPHID2 register bit assignments Name Description [31:08] Read undefined [07:04] Revision These bits read back as 0x1 [03:00] Designer1 These bits read back as 0x0 8.6.20 VICPERIPHID3 register The read-only VICPERIPHID3 register, with address offset of 0xFEC, is hard-coded, and the fields within the register determine the reset value.Table 44 shows the bit assignments...
Page 102: Vicpcellid2 Register
CPU subsystem_Vectored interrupt controller (VIC) RM0082 8.6.24 VICPCELLID2 register The read-only VICPCELLID2 register, with address offset 0xFF8, is hard-coded and the fields within the register determine the reset value. Table 47 shows the bit assignments for this register Table 47. VICPCELLID2 register bit assignments Name Description...
Page 103: Bus Interconnection Matrix
RM0082 Bus interconnection matrix Bus interconnection matrix The SoC interconnection matrix scheme is given Table 49 Table Table 49. SoC interconnection matrix scheme MemCtr#0 MemCtr#1 MemCtr#2 lcm5 REQ1 REQ2 MemCtr#3 lcm7 REQ1 REQ2 REQ3 REQ4 MemCtr#4 lcm8 REQ1 REQ2 Ras_I Ras_M Ras_G1 Ras_G2...
Page 104: Icm
Bus interconnection matrix RM0082 The AMBA system has ten programmable Multi-layer Interconnection Matrix (ICM). The ICM allows multiple master layers to access a slave (See Figure Figure 6. ICM block diagram MASTER (Layer 0) SLAVE AHB MASTER (Layer N) priority Arbiter A layer is referred to as one or more masters that complete together with one master winning ownership of the slave.
Page 105: Table 52. Icm Slaves (Targets)
RM0082 Bus interconnection matrix Table 52. ICM slaves (Targets) Sbs_LowSpeed Sbs_Application Sbs_Basic Sbs_Highspeed MemCtr#2 (MPMC) Ras_F MemCtr#3 (MPMC) MemCtr#4 (MPMC) In the Miscellaneous register bank are allocated eight register (ICM_x_ARB_CFG) one for each ICM. These registers have all the same layout: ●...
Page 106: Ddr Memory Controller (Mpmc)
DDR memory controller (MPMC) 10.1 Overview SPEAr300 integrates a high performances multi-port memory controller able to support DDR-Mobile and DDR2 double data rate memory devices. The multi-port architecture ensures memory is shared efficiently among different high-bandwidth client modules. It offers 6 internal ports. One of them is reserved to registers access during the controller initialization while the other five are used to access the external memory.
Page 107: Table 54. Internal Signals
RM0082 DDR memory controller (MPMC) Table 53. External memory Interface signals (continued) Signal name Direction Description Differential memory data strobe negative line. Drove during DDR_nDQS_(1:0) Bidir. write transaction and received from memory device during read transfer. DDR_CLKEN Memory clock enable (active high) DDR_CS_(1:0) Memory chip select (active low) DDR_RAS...
Page 108: Features Overview
DDR memory controller (MPMC) RM0082 10.3 Features overview The memory controller includes the following main features: ● Multi channel AHB interfaces: – Five independent AHB ports. – Separate AHB memory controller programming interface. – Support all AHB burst types. – Lock transaction are not supported.
Page 109: Main Block Description
RM0082 DDR memory controller (MPMC) 10.4 Main block description The multi-port memory controller supports high memory bandwidth utilization and an efficient arbitration scheme for high priority agent requests. The memory controller architecture consists of the following main sub-blocks: ● AHB port interfaces. ●...
Page 110: Ahb-Memory Controller Interfaces
DDR memory controller (MPMC) RM0082 10.4.1 AHB-Memory controller interfaces The Memory Controller core interfaces with 5 AHB data ports and 1 AHB register port. The AHB data ports function as AHB slaves to external AHB masters such as CPUs, DMAs, DSPs, and other peripherals.
Page 111 RM0082 DDR memory controller (MPMC) Port FIFO depths Each data port contains a read, a write and a command FIFO. The depth of each buffer in each port is listed in Table 55: Configured AHB settings. Error detection When an illegal operational condition is detected on a new AHB transaction entering the port, the port responds with an ERROR.
Page 112: Table 55. Configured Ahb Settings
DDR memory controller (MPMC) RM0082 AHB port. A deeper command FIFO is only useful in situations when the master issues several very short WRITE bursts. In this case, the commands and the associated data will be completely captured in the command and write FIFOs and the bus will be free to start other operations.
Page 113 RM0082 DDR memory controller (MPMC) During initialization, it is recommended that both resets be asserted simultaneously. The Memory Controller core reset should be removed first, followed by the port reset. The reset should be asserted for at least 5 cycles. AHB register port The AHB-Memory Controller Interface contains a special register port for converting AHB register addresses to Memory Controller core register addresses.
Page 114: Figure 9. Wrapx Effective Transaction
DDR memory controller (MPMC) RM0082 means that an AHB WRAP instruction is divided into two Memory Controller core transactions, one for the non-wrapped portion of the transaction and one for the wrapped portion. The starting address determines whether the WRAP transaction will actually wrap or not.
Page 115: Table 56. Read/Write Data Alignment - Little Endian
RM0082 DDR memory controller (MPMC) The first command is issued when the AHB request is decoded. Subsequent read commands are issued when the last word of data has been delivered from the Memory Controller core to the AHB port. Subsequent WRITE commands are issued after the last WRITE data word of the last command has been transferred from the AHB bus to the Memory Controller core.
Page 116: Table 57. Read/Write Data Alignment - Big Endian
DDR memory controller (MPMC) RM0082 Table 56. READ/WRITE data alignment - Little Endian (continued) Transaction type Address Data alignment - little endian BYTE 0x--Aa------------ BYTE 0xAa-------------- HALF WORD 0x------------BbAa HALF WORD 0x--------BbAa---- HALF WORD 0x----BbAa-------- HALF WORD 0xBbAa------------ WORD 0x--------DdCcBbAa WORD 0xDdCcBbAa-------- Table 57.
Page 117: Table 58. Ahb-Memory Controller Translation Example
RM0082 DDR memory controller (MPMC) Table 58. AHB-Memory controller translation example AHBx transaction Memory controller transaction Burst size Bytes per beat Address Address Length AHBx (AHBx HSIZE) HBURST AHBx Byte, half-word or SINGLE AHBx Address 1 x (AHBx HSIZE) Address word AHBx Byte, half-word or...
Page 118: Arbiter
DDR memory controller (MPMC) RM0082 Controller core. The length is a defined quantity that is specified at the beginning of the transaction. For WRITE transactions, the AHB port forwards the data from the AHBx HWDATA signals provided by the AHB master to the Memory Controller core. If the WRITE transaction is early burst-terminated, the port will continue the data stream, but issue masked WRITE data for the duration of the transaction instead.
Page 119: Dram Command Processing
RM0082 DDR memory controller (MPMC) should also be so large to hold enough words to consume data for a single write transaction related to the bus. The data may actually be written into the buffers from the bus at a later time, depending on the priority of the request and the number of transactions in the Command Queue.
Page 120: Multi-Port Arbiter
DDR memory controller (MPMC) RM0082 If the page for the new transaction is already open, the current transaction will be interrupted at the next natural burst boundary of the DRAM device. If the page is not currently open instead, the new request will be placed at the top of the command queue while its page is prepared.
Page 121: Arbitration Overview
RM0082 DDR memory controller (MPMC) The Arbiter logic routes READ data from the Memory Controller core to the appropriate port. The requesting port is assumed to be able to receive the data. WRITE data from each port is connected directly to its own WRITE data interface inside the Memory Controller core, allowing the ports to independently pass them to the Memory Controller core buffers.
Page 122: Understanding Port Priority
DDR memory controller (MPMC) RM0082 Table 59. Round-Robin operation example Port addressed Port requesting Command Winner of Value of counter Cycle by an arbitration queue full? arbitration at the next cycle counter None None None 10.5.3 Understanding port priority For AHB ports, the priority is associated with a port and each port has separate priority parameter for READ and WRITE operations.
Page 123: Figure 10. Weighted Round-Robin Priority Group Structure
RM0082 DDR memory controller (MPMC) Figure 10. Weighted round-robin priority group structure Priority Group 0 ahb0_priority0_relative_priority ahb1_priority0_relative_priority Priority 0 ahb2_priority0_relative_priority Commands … abhX_priority0_relative_priority Priority Group 1 Priority 1 ahb0_priority1_relative_priority … Commands ahbX_priority1_relative_priority Ports Priority Group 2 Priority 2 ahb0_priority2_relative_priority … Commands ahbX_priority2_relative_priority Priority Group Z...
Page 124: Understanding Port Ordering
DDR memory controller (MPMC) RM0082 Table 60. Relative priority example Parameter System A ahb0_priority0_relative_priority ahb1_priority0_relative_priority ahb2_priority0_relative_priority ahb3_priority0_relative_priority For this system, port 0 will be processed 1/(1+2+3+4) = 1/10 of the time and Port 3 will be processed 4/ (1+2+3+4) = 4/10 of the time. However, if Port 2 is not actively requesting, then port 0 will be processed 1/(1+2+4) = 1/7 of the time and port 3 will be processed 4/(1+2+4) = 4/7 of the time.
Page 125: Weighted Round-Robin Arbitration Summary
RM0082 DDR memory controller (MPMC) Table 61. Port ordering example Parameter System B System C ahb0_port_ordering ahb1_port_ordering ahb2_port_ordering ahb3_port_ordering ahb4_port_ordering ahb5_port_ordering ahb6_port_ordering ahb7_port_ordering Port Scan Order P5-P7-P6-P0-P1-P2-P3-P4 P1-P6-P7-P5-P0-P2-P3-P4 If every port ordering parameters are set to the same value, the scan order will default to the numbered port order.
Page 126: Table 63. System D Operation
DDR memory controller (MPMC) RM0082 Table 63. System D operation Ports requesting Next counter Arbitration Cycle Next scan order winner P0-P1-P2-P3 P0-P1-P2-P3 P0-P1-P2-P3 P0-P1-P2-P3 P1-P2-P3-P0 P1-P2-P3-P0 P1-P2-P3-P0 P2-P3-P0-P1 P2-P3-P0-P1 P3-P0-P1-P2 P0-P1-P2-P3 P0-P1-P2-P3 P0-P1-P2-P3 P0-P1-P3-P2 If the same system also contains two ports that only can request at priority level 1, the system behavior will be slightly altered.
Page 127: Priority Relaxing
RM0082 DDR memory controller (MPMC) Table 65. System E operation Port Requesting Next Counter Arbitration Cycle Next Scan Order Winner P0 P1 P2 P3 P4 P5 P0 P1 P2 P3 P4 P5 Priority 0: P0-P1-P2-P3 Priority 1: P4-P5 P0-P1-P2-P3-P4-P5 P0-P1-P2-P3-P4-P5 P0-P1-P3-P2-P4-P5 P0-P1-P3-P2-P4-P5 P0-P1-P3-P2-P4-P5...
Page 128: Table 66. System F Specifications
DDR memory controller (MPMC) RM0082 priority relax counters could reach their specified value simultaneously. In this case, the lower priority command will be arbitrated first and the higher priority command afterward. This situation could modify the arbitration latency slightly, causing it to be longer than the expected value in the priority relax parameter.
Page 129: Port Pairing
RM0082 DDR memory controller (MPMC) Table 67. System F operation with priority relaxing (continued) Ports Requesting Next Counter Relaxed Arbitration Cycle Next Scan Order Ports Winner P0-P1-P3-P2 Y Y P0, P5 P4-P5 P0-P1-P3-P2 P4-P5 P0-P1-P3-P2 Y Y P4 P5-P4 P0-P1-P3-P2 Y Y Y P5-P4 P0-P1-P3-P2...
Page 130: Table 68. System G Specifications
DDR memory controller (MPMC) RM0082 Let us consider System G as described inTable 68. Again, to simplify the command queue is considered to never be full, commands from ports 0, 1, 2 and 3 are only received at priority level 0 and commands from ports 4 and 5 are always at priority 1. However, now ports P0 - P1, and ports P4 - P5 are paired.
Page 131: Error Conditions
RM0082 DDR memory controller (MPMC) Table 69. System G operation (continued) Ports Requesting Next Counter Arbitration Cycle Next Scan Order Winner P0 P1 P2 P3 P4 P5 P0 P1 P2 P3 P4 P5 P2-P0-P1-P3 P5-P4 P2-P0-P1-P3 P5-P4 P2-P0-P1-P3 P5-P4 P0-P1-P3-P2 P5-P4 P0-P1-P3-P2 P5-P4...
Page 132: Core Command Queue With Placement Logic
DDR memory controller (MPMC) RM0082 10.6 Core command queue with placement logic The Memory Controller core contains a command queue that accepts commands from the Arbiter. This command queue uses a placement algorithm to determine the order in which commands will be executed in the Memory Controller core. The placement logic follows many rules to determine where new commands should be inserted into the queue, relative to the contents of the command queue at the time.
Page 133 RM0082 DDR memory controller (MPMC) The behavior of commands of different types from the same source ID is dependent on the user configuration. For Memory Controller, the placement of new READ/WRITE commands that collide in terms of source ID with existing entries in the command queue will only depend on other commands of the same type, not on different types.
Page 134: Command Execution Order After Placement
DDR memory controller (MPMC) RM0082 be possible if there are no priority, source ID, WRITE buffer or address collisions or conflicts with other commands in the command queue. Every bank splitting feature could be enabled through the bank_split_en parameter. Read/Write grouping The memory suffers a small timing overhead when switching from READ to WRITE mode.
Page 135: Low Power Operation
RM0082 DDR memory controller (MPMC) priority of the associated command will be decremented by one (lower priority commands are executed first). This increases the likelihood that this command will move to the top of the command queue and be executed. Note: This command does not move relative positions in the command queue when it ages;...
Page 136: Low Power Mode Control
DDR memory controller (MPMC) RM0082 Memory Controller will only attempt to gate the clock if it is configured for mobile device operation. For non-mobile memory devices in this low power mode, the Memory Controller will operate identically to the Memory Power-Down mode without the clock gating (Mode 1).
Page 137 RM0082 DDR memory controller (MPMC) There are 4 counters to full cover the 5 low power modes. There are separate counters for each of the three memory self-refresh low power modes (Modes 3, 4 and 5). Memory Power-Down mode (Mode 1) and Memory Power-Down with Memory Clock Gating mode (Mode 2) share the same counter.
Page 138: Table 70. Low Power Mode Parameters
DDR memory controller (MPMC) RM0082 mode. There will be at least a 15 cycle delay before the component being either fully operational or enters the new low power mode. Register programming The low power modes of the Memory Controller are controlled by the lowpower_control and lowpower_auto_enable parameters.
Page 139: Table 71. Low Power Mode Controls
RM0082 DDR memory controller (MPMC) Table 71. Low power mode controls Low Power Mode Counter Memory Power-Down (Mode 1) lowpower_power_down_cnt Memory Power-Down with Memory Clock Gating (Mode 2) lowpower_power_down_cnt Memory Self-Refresh (Mode 3) lowpower_self_refresh_cnt Memory Self-Refresh with Memory Clock Gating (Mode 4) lowpower_external_cnt Memory Self-Refresh with Memory and Controller Clock Gating lowpower_internal_cn...
Page 140: Additional Features
DDR memory controller (MPMC) RM0082 Refresh masking Regular refresh commands will be issued at the same intervals as the Memory Controller is operating normally, is idle, or is in any of the low power modes. However, for memory arrays with multiple chip selects, the Memory Controller can mask refreshes during any of the low power modes.
Page 141: Mobile Devices Dqs
RM0082 DDR memory controller (MPMC) Reading the out-of-range parameters will trigger the Memory Controller to empty these parameters and allow them to store out-of-range access information for future errors. The interrupt should be acknowledged by setting bit 0 of the int_ack parameter to 1'b1, which will in turn cause bit 0 of the int_status parameter to be cleared to 1'b0.
Page 142: User-Defined Registers
DDR memory controller (MPMC) RM0082 10.8.4 User-defined registers Memory Controller contains two user-defined parameters. These register-width size parameters hold user-defined values that will be available as output signals param_user_def_reg_X (X is 0 or 1) at the Memory Controller core (stp_memcd) level. These parameters have no effect on the Memory Controller except that utilizing addresses in the register map.
Page 143: Maximum Address Space
RM0082 DDR memory controller (MPMC) 10.9.2 Maximum address space The maximum user address range is determined by the width of the memory datapath, the number of chip select pins, and the address space of the DRAM device. The maximum amount of memory can be calculated by the following formula: Max Memory Bytes = ChipSelects x 2Address x NumBanks x DPWidthBytes For this Memory Controller, the maximum values for these fields are as follows: ●...
Page 144: Dcc Tuning Timing
DDR memory controller (MPMC) RM0082 10.10 DCC tuning timing The command and address for the transaction are sent from the memory controller coincident with the falling edge of the memory controller clock. Since the clock, command, and address signals will all have roughly the same pad and flight delays to travel to the memory, the rising edge of the clock at the memory will be centered with the command and address signals, allowing reliable capture.
Page 145: External Pin Connection Of Ddr Interface In Spear300
However, to accommodate the skew of the memory devices, it may be necessary to open the gate a 1/2-cycle sooner or later. Adjusting the value of caslat_lin_gate modifies the gate opening by this factor. 10.11 External pin connection Of DDR interface in SPEAr300 Refer to Chapter 5: Pin description.
Page 146: Table 74. Mt47H128M8-3 (Ddr2@333 Mhz Cl5) Initialization Table
DDR memory controller (MPMC) RM0082 Table 74. MT47H128M8-3 (DDR2@333 MHz cl5) initialization table Register name Value Register name Value MEM0_CTL 0x01010101 MEM55_CTL 0x00000000 MEM1_CTL 0x00000101 MEM56_CTL 0x5B1C00C8 MEM2_CTL 0x01000000 MEM57_CTL 0x00C8002E MEM3_CTL 0x00000101 MEM58_CTL 0x00000000 MEM4_CTL 0x00000101 MEM59_CTL 0x00000043 MEM5_CTL 0x01000000 MEM60_CTL 0x00000000...
Page 147: Table 75. Mt46H6M16Lf-6(Low Power Ddr @166 Mhz Cl3) Initialization Table
RM0082 DDR memory controller (MPMC) Table 74. MT47H128M8-3 (DDR2@333 MHz cl5) initialization table (continued) Register name Value Register name Value MEM35_CTL 0x0000023F MEM90_CTL 0x00000000 MEM36_CTL 0x00050A00 MEM91_CTL 0x00000000 MEM37_CTL 0x0D000000 MEM92_CTL 0x00000000 MEM38_CTL 0x00001302 MEM93_CTL 0x00000000 MEM39_CTL 0x00001E1E MEM94_CTL 0x00000000 MEM40_CTL 0x7F000000 MEM95_CTL...
Page 148 DDR memory controller (MPMC) RM0082 Table 75. MT46H6M16LF-6(Low Power DDR @166 MHz cl3) initialization table Register name Value Register n ame Value MEM12_CTL 0x02020102 MEM67_CTL 0x00B70000 MEM13_CTL 0x03020202 MEM68_CTL 0x003C00F4 MEM14_CTL 0x02040202 MEM69_CTL 0x00000000 MEM15_CTL 0x00000002 MEM70_CTL 0x00000000 MEM16_CTL 0x00000000 MEM71_CTL 0x00000000 MEM17_CTL...
Page 149: Register Interface
2 Byte Boundary 17 to 128 4 bytes 4 Byte Boundary 10.13.2 MPMC base address In SPEAr300 Base address = 0xFC60.0000 10.13.3 Register map Note: The address refers to the register address reg_addr, not a signal on the command address line.
Page 150: Table 77. Registers Overview
DDR memory controller (MPMC) RM0082 Table 77. Registers overview Mem. CTRL Register name Offset core Reg. Type Parameter(s) Address AHB2_FIFO_TYPE_REG AHB1_FIFO_TYPE_REG MEM0_CTL 0x00 0x00 AHB0_FIFO_TYPE_REG ADDR_CMP_EN AHB4_FIFO_TYPE_REG MEM1_CTL 0x04 0x01 AHB3_FIFO_TYPE_REG BANK_SPLIT_EN AUTO_REFRESH_MODE MEM2_CTL 0x08 0x02 AREFRESH DLL_BYPASS_MODE DLLLOCKREG MEM3_CTL 0x0C 0x03 DDRII_SDRAM_MODE...
Page 151 RM0082 DDR memory controller (MPMC) Table 77. Registers overview (continued) Mem. CTRL Register name Offset core Reg. Type Parameter(s) Address RTT_0 OUT_OF_RANGE_TYPE MEM10_CTL 0x28 0x0A ODT_WR_MAP_CS1 ODT_WR_MAP_CS0 AHB0_R_PRIORITY AHB0_PORT_ORDERING MEM11_CTL 0x2C 0x0B ADDR_PINS RTT_PAD_TERMINATION AHB1_W_PRIORITY AHB1_R_PRIORITY MEM12_CTL 0x30 0x0C AHB1_PORT_ORDERING AHB0_W_PRIORITY AHB3_PORT_ORDERING AHB2_W_PRIORITY...
Page 152 DDR memory controller (MPMC) RM0082 Table 77. Registers overview (continued) Mem. CTRL Register name Offset core Reg. Type Parameter(s) Address AHB0_PRIORITY6_RELATIVE_PRIORITY AHB0_PRIORITY5_RELATIVE_PRIORITY MEM21_CTL 0x54 0x15 AHB0_PRIORITY4_RELATIVE_PRIORITY AHB0_PRIORITY3_RELATIVE_PRIORITY AHB1_PRIORITY2_RELATIVE_PRIORITY AHB1_PRIORITY1_RELATIVE_PRIORITY MEM22_CTL 0x58 0x16 AHB1_PRIORITY0_RELATIVE_PRIORITY AHB0_PRIORITY7_RELATIVE_PRIORITY AHB1_PRIORITY6_RELATIVE_PRIORITY AHB1_PRIORITY5_RELATIVE_PRIORITY MEM23_CTL 0x5C 0x17 AHB1_PRIORITY4_RELATIVE_PRIORITY AHB1_PRIORITY3_RELATIVE_PRIORITY AHB2_PRIORITY2_RELATIVE_PRIORITY AHB2_PRIORITY1_RELATIVE_PRIORITY...
Page 153 RM0082 DDR memory controller (MPMC) Table 77. Registers overview (continued) Mem. CTRL Register name Offset core Reg. Type Parameter(s) Address CASLAT_LIN_GATE MEM34_CTL 0x88 0x22 CASLAT_LIN APREBIT MAX_ROW_REG MAX_COL_REG MEM35_CTL 0x8C 0x23 INITAREF COMMAND_AGE_COUNT WRR_PARAM_VALUE_ERR MEM36_CTL 0x90 0x24 TDAL Q_FULLNESS TFAW OCD_ADJUST_PUP_CS_0 MEM37_CTL 0x94...
Page 154 DDR memory controller (MPMC) RM0082 Table 77. Registers overview (continued) Mem. CTRL Register name Offset core Reg. Type Parameter(s) Address AHB3_WRCNT MEM50_CTL 0xC8 0x32 AHB3_RDCNT AHB4_WRCNT MEM51_CTL 0xCC 0x33 AHB4_RDCNT MEM52_CTL 0xD0 0x34 This register intentionally blank. MEM53_CTL 0xD4 0x35 This register intentionally blank.
Page 155 RM0082 DDR memory controller (MPMC) Table 77. Registers overview (continued) Mem. CTRL Register name Offset core Reg. Type Parameter(s) Address MEM78_CTL 0x138 0x4E This register intentionally blank. MEM79_CTL 0x13C 0x4F This register intentionally blank. MEM80_CTL 0x140 0x50 This register intentionally blank. MEM81_CTL 0x144 0x51...
Page 156: Register Description
DDR memory controller (MPMC) RM0082 Table 77. Registers overview (continued) Mem. CTRL Register name Offset core Reg. Type Parameter(s) Address EMRS2_DATA_1 MEM104_CTL 0x1A0 0x68 EMRS2_DATA_0 LOWPOWER_INTERNAL_CNT MEM105_CTL 0x1A4 0x69 LOWPOWER_EXTERNAL_CNT LOWPOWER_REFRESH_HOLD MEM106_CTL 0x1A8 0x6A LOWPOWER_POWER_DOWN_CNT TCPD MEM107_CTL 0x1AC 0x6B LOWPOWER_SELF_REFRESH_CNT MEM108_CTL 0x1B0 0x6C...
Page 157: Mem1_Ctl Register
RM0082 DDR memory controller (MPMC) Table 78. MEM0_CTL register bit assignments (continued) Reset Name Range Description value Reserved. Read undefined. Write should be [07:04] zero. Enable address collision detection for CMD [03:00] ADDR_CMP_EN 0x0-0x1 queue placement logic. 10.13.6 MEM1_CTL register Table 79.
Page 158: Mem3_Ctl Register
DDR memory controller (MPMC) RM0082 10.13.8 MEM3_CTL register Table 81. MEM3_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:25] zero. DLL_BYPASS_MO [24] 0x0 - 0x1 Enable the DLL bypass feature of the controller. Reserved.
Page 159: 10.13.10 Mem5_Ctl Register
RM0082 DDR memory controller (MPMC) 10.13.10 MEM5_CTL register Table 83. MEM5_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:25] zero. ODT_ADD_TURN_C 0x0 - Enable extra turn-around clock between back-to- [24] LK_EN back READs/WRITEs to different chip selects. Reserved.
Page 160: Table 85. Mem7_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.12 MEM7_CTL register Table 85. MEM7_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:25] zero. [24] START 0x0 - 0x1 Begin CMD processing in the controller. Reserved. Read undefined. Write should be [23:17] zero.
Page 161: Table 87. Mem9_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) 10.13.14 MEM9_CTL register Table 87. MEM9_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:26] - zero. ODT Chip Select 1 map for READs. [25:24] ODT_RD_MAP_CS1 0x0 0x0 - 0x3 Determines which chip(s) will have termination when a read occurs on chip 1.
Page 162: Table 89. Mem11_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 Table 88. MEM10_CTL register bit assignments (continued) Reset Name Range Description value Reserved. Read undefined. Write should be [07:02] - zero. ODT Chip Select 0 map for WRITEs. [01:00] ODT_WR_MAP_CS0 0x0 - 0x3 Determines which chip(s) will have termination when a write occurs on chip 0.
Page 163: Table 91. Mem13_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) Table 90. MEM12_CTL register bit assignments (continued) Reset Name Range Description value AHB1_PORT_ORDE [10:08] 0x0 - 0x7 Reassigned port order for port 1. RING Reserved. Read undefined. Write should be [07:03] - zero. [02:00] AHB0_W_PRIORITY 0x0 - 0x7 Priority of write commands from port 0.
Page 164: Table 93. Mem15_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 Table 92. MEM14_CTL register bit assignments (continued) Reset Name Range Description value Reserved. Read undefined. Write should [07:03] - be zero. [02:00] AHB3_R_PRIORITY 0x0 - 0x7 Priority of read commands from port 3. 10.13.20 MEM15_CTL register Table 93.
Page 165: Table 96. Mem18_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) Table 95. MEM17_CTL register bit assignments (continued) Reset Name Range Description value Reserved. Read undefined. Write should be [07:03] - zero. Encoded CAS latency sent to DRAMs during [02:00] CAS_LATENCY 0x0 - 0x7 initialization. 10.13.23 MEM18_CTL register Table 96.
Page 166: Table 98. Mem20_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.25 MEM20_CTL register Table 98. MEM20_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:28] - zero. AHB0_PRIORITY2_RE Relative priority of priority 2 CMDs from port [27:24] 0x0 - 0xF LATIVE_PRIORITY Reserved.
Page 167: Table 100. Mem22_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) 10.13.27 MEM22_CTL register Table 100. MEM22_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write [31:28] - should be zero. AHB1_PRIORITY2_RELATIVE_ Relative priority of priority 2 CMDs [27:24] 0x0 - 0xF PRIORITY from port 1.
Page 168: Table 102. Mem24_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.29 MEM24_CTL register Table 102. MEM24_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:28] - zero. AHB2_PRIORITY2_RE Relative priority of priority 2 CMDs from port [27:24] 0x0 - 0xF LATIVE_PRIORITY Reserved.
Page 169: Table 104. Mem26_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) 10.13.31 MEM26_CTL register Table 104. MEM26_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:28] - zero. AHB3_PRIORITY2_RE Relative priority of priority 2 CMDs from port [27:24] 0x0 - 0xF LATIVE_PRIORITY Reserved.
Page 170: Table 106. Mem28_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.33 MEM28_CTL register Table 106. MEM28_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:28] - zero. AHB4_PRIORITY2_R [27:24] 0x0 - 0xF Relative priority of priority 2 CMDs from port 4. ELATIVE_PRIORITY Reserved.
Page 171: Table 108. Mem30_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) 10.13.35 MEM30_CTL register Table 108. MEM30_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:04] - zero. AHB4_PRIORITY7_REL Relative priority of priority 7 CMDs from port [03:00] 0x0 - 0xF ATIVE_PRIORITY 10.13.36 MEM31_CTL/MEM32_CTL/MEM33_CTL register Table 109.
Page 172: Table 111. Mem35_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.38 MEM35_CTL register Table 111. MEM35_CTL register bit assignments Reset Name Range Description value [31:28] - Reserved. Read undefined. Write should be zero. Maximum width of memory addresses bus. [27:24] MAX_ROW 0x0 - 0xF READ-ONLY [23:20] - Reserved.
Page 173: Table 114. Mem38_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) Table 113. MEM37_CTL register bit assignments (continued) Reset Name Range Description value Reserved. Read undefined. Write should be [23:21] - zero. OCD_ADJUST_PUP OCD pull-up adjust setting for DRAMs for chip [20:16] 0x0 - 0x1F _CS0 select 0.
Page 174: Table 116. Mem40_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 Table 115. MEM39_CTL register bit assignments (continued) Reset Name Range Description value [07] Reserved. Read undefined. Write should be zero. DLL_DQS_DELA Fraction of a cycle to delay the dqs signal from the [06:00] 0x0 - 0x7F DRAMs for dll_rd_dqs_slice 0 during READs.
Page 175: Table 119. Mem43_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) 10.13.46 MEM43_CTL register Table 119. MEM43_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:26] - zero. AHB1_PRIORITY Counter value to trigger priority relax on port [25:16] 0x000 0x000 - 0x3FF _RELAX Reserved.
Page 176: Table 122. Mem46_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.49 MEM46_CTL register Table 122. MEM46_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:26] - zero. OUT_OF_RANGE Length of CMD that caused an Out-of-Range [25:16] 0x000 0x000 - 0x3FF _LENGTH interrupt.
Page 177: Table 125. Mem49_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) 10.13.52 MEM49_CTL register Table 125. MEM49_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:26] - zero. Number of bytes for an INCR WRITE CMD on [25:16] AHB2_WRCNT 0x000 0x000 - 0x7FF port 2.
Page 178: Table 128. Mem52_Ctl/Mem53_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.55 MEM52_CTL/MEM53_CTL register Table 128. MEM52_CTL/MEM53_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:00] - zero. 10.13.56 MEM54_CTL register Table 129. MEM54_CTL register bit assignments Reset Name Range Description value Reserved.
Page 179: Table 133. Mem58_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) 10.13.60 MEM58_CTL register Table 133. MEM58_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:16] - zero. [15:00] VERSION 0x2041 Controller version number. READ-ONLY 10.13.61 MEM59_CTL register Table 134. MEM59_CTL register bit assignments Reset Name Range...
Page 180: Table 137. Mem62_Ctl/Mem63_Ctl/Mem64_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.64 MEM62_CTL/MEM63_CTL/MEM64_CTL register Table 137. MEM62_CTL/MEM63_CTL/MEM64_CTL register bit assignments Reset Name Range Description value [31:00] - Reserved. Read undefined. Write should be zero. 10.13.65 MEM65_CTL register Table 138. MEM65_CTL register bit assignments Reset Name Range Description value Reserved.
Page 181: Table 141. Mem68_Ctl Register Bit Assignments
Table 143. MEM[98-99]_CTL register bit assignments Reset Name Range Description value [31:00] user_def_reg(x) 0x0 0x0 - 0xFFFF_FFFF User defined register. Note: Only the USER_DEF_REG(0) bit 0 is used in SPEAr300. All the other bits are reserved. Doc ID 018672 Rev 1 181/844...
Page 182: Table 144. Mem100_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 10.13.71 MEM100_CTL register Table 144. MEM100_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:25] - zero. enable_quick_sref Allow user to interrupt memory initialization to [24] 0x0 - 0x1 resh enter self refresh mode.
Page 183: Table 146. Mem102_Ctl Register Bit Assignments
RM0082 DDR memory controller (MPMC) 10.13.73 MEM102_CTL register Table 146. MEM102_CTL register bit assignments Reset Name Range Description value Reserved. Read undefined. Write should be [31:29] - zero. lowpower_auto_enab Enables automatic entry into the low power [28:24] 0x0 - 0x1F mode on idle.
Page 184: Table 149. Mem105_Ctl Register Bit Assignments
DDR memory controller (MPMC) RM0082 Table 148. MEM104_CTL register bit assignments (continued) Reset Name Range Description value Reserved. Read undefined. Write [15] should be zero. [14:00] emrs2_data0 0x0000 0x0000 - 0x7FFF EMRS2 data for chip select 0. 10.13.76 MEM105_CTL register Table 149.
Page 185: Table 153. Memory Controller Parameters
RM0082 DDR memory controller (MPMC) 10.14 Summary of memory controller parameters Note: The table below gives a description of the parameters referred to throughout this chapter. To fully understand the concepts related to each parameter, please refer to the relevant sections of the document.
Page 186 DDR memory controller (MPMC) RM0082 Table 153. Memory controller parameters (continued) Parameter Description Holds the number of bytes to be responded to AHB port X after an INCR READ AHB command. The AHB logic will subdivide an INCR request into Memory Controller core commands of the size of this parameter.
Page 187 RM0082 DDR memory controller (MPMC) Table 153. Memory controller parameters (continued) Parameter Description Sets the mode to be performed as the automatic refresh will occur. If auto_refresh_mode is set and a refresh is required to memory, the Memory Controller will either delay this refresh until the end of the current transaction has been reached (if the transaction is fully contained inside a single page), or until the current transaction hits the auto_refresh_mode [0]...
Page 188 DDR memory controller (MPMC) RM0082 Table 153. Memory controller parameters (continued) Parameter Description Adjusts the data capture gate open time by half-cycle expressed increments number. This parameter is set differently than caslat_lin one whether there are fixed offsets in the flight path between the memories and the Memory Controller for clock gating.
Page 189 RM0082 DDR memory controller (MPMC) Table 153. Memory controller parameters (continued) Parameter Description Sets the mask that determines which chip select pins are active, with each bit representing a different chip select. The user address chip select field will be mapped into the active chip selects indicated by this parameter in ascending order from lowest to highest.
Page 190 DDR memory controller (MPMC) RM0082 Table 153. Memory controller parameters (continued) Parameter Description Shows the actual number of delay elements used to capture one full dll_lock [9:0] clock cycle. This parameter is automatically updated every time a refresh operation is performed. This parameter is read-only. Sets the number of delay elements to place in the master delay line to dll_start_point [9:0] start searching for lock in master DLL.
Page 191 RM0082 DDR memory controller (MPMC) Table 153. Memory controller parameters (continued) Parameter Description When this bit is set, the memory initialization sequence will be interrupted and self-refresh mode will be entered. enable_quick_srefresh [0] 1'b0 - Continue memory initialization. 1'b1 - Interrupts memory initialization and enter self-refresh mode. Controls the mode and timing the WRITE commands are issued toward the DRAM devices.
Page 192 DDR memory controller (MPMC) RM0082 Table 153. Memory controller parameters (continued) Parameter Description Controls whether an interruption of a combined READ with auto pre- charge command, by another READ command toward the same bank before the current READ command has been completed, is allowed. intrptreada [0] 1'b0 - Interrupt Disable.
Page 193 RM0082 DDR memory controller (MPMC) Table 153. Memory controller parameters (continued) Parameter Description Counts the number of idle cycles before memory self-refresh with lowpower_internal_cnt memory and controller clock gating low power mode. [15:0] Please refer to Section 10.7 on page 135 for more details.
Page 194 DDR memory controller (MPMC) RM0082 Table 153. Memory controller parameters (continued) Parameter Description Sets the off-chip driver (OCD) pull-up adjustment settings for the DRAM devices. The Memory Controller will issue OCD adjust commands to the DRAM devices during power up. ocd_adjust_pup_cs [4:0] Bits 3:0 - Number of OCD adjust commands to be issued.
Page 195 RM0082 DDR memory controller (MPMC) Table 153. Memory controller parameters (continued) Parameter Description Holds the type of command that caused an out-of-range interrupt request to the memory devices. This parameter is read-only. out_of_range_type [1:0] For more information on out-of-range address checking, refer to Section 10.8 on page 140.
Page 196 DDR memory controller (MPMC) RM0082 Table 153. Memory controller parameters (continued) Parameter Description Enables registered DIMM operations to control the address and command pipeline of the Memory Controller. reg_dimm_enable [0] 1'b0 - Normal operation 1'b1 - Enable registered DIMM operation. Defines the On-Die termination resistance for all DRAM devices.
Page 197 RM0082 DDR memory controller (MPMC) Table 153. Memory controller parameters (continued) Parameter Description With this parameter set to 'b0, the Memory Controller will not issue any command to the DRAM devices or respond to any signal activity except for reading and writing parameters. Once this parameter is set to 'b1, the Memory Controller will respond to inputs from the device.
Page 198 DDR memory controller (MPMC) RM0082 Table 153. Memory controller parameters (continued) Parameter Description Defines the DRAM cycles between refresh commands. tref [13:0] Please refer to Section 10.8 on page 140 to have more details. Enables internal refresh commands. If command refresh mode is configured, then refresh commands will be issued based on the internal tref counter and any refresh commands sent through the command tref_enable [0]...
Page 199 RM0082 DDR memory controller (MPMC) Table 153. Memory controller parameters (continued) Parameter Description Sets the delay for the ddr_close signal to ensure correct data capture in the I/O logic. wr_dqs_shift [6:0] Each increment of this parameter adds a delay of 1/128 of the system clock.
Page 200 DDR memory controller (MPMC) RM0082 6. This parameter must be static during normal operation. While this parameter defaults to 0x0, the minimum valid value is 0x1. The user should program this parameter to a non-zero value during initialization. 7. SPEAR™ Memory Controller does not support the MOBILE feature in DDR2 mode. Therefore, setting this bit in conjunction with the DDR2 mode enable bit (ddrii_sdram_mode) will cause an interrupt.
Page 201: Clock & Reset System
RM0082 Clock & reset system Clock & reset system The Clock system block is able to generate all clocks necessary at the chip. The main clocks, at default operative frequency, are: ● CPU_CLK @ 333 MHz for the CPUs. ● HCLK @ 166 MHz for AHB Bus and AHB peripherals.
Page 202: Table 154. Jitter At Pll Output Clock
Clock & reset system RM0082 11.1 Clock generation scheme Figure 13. Clock generation scheme Min 333 MHz CPU_CLK Min 166 MHz DIV1/ HCLK PLL1 DIV2/ DIV3 Min 83 MHz DIV1/ PCLK DIV2/ DIV3 333 MHz DDR_CLK 24MHz PLL2 CLK12MHz PLL3 CLK30MHz CLK48MHz 32.768KHz...
Page 203: Figure 14. Processor Clock
RM0082 Clock & reset system The B parameter (random jitter) is the value of one sigma of this normal distribution, while A parameter is the deterministic jitter. Single period jitter can be defined as the difference of the Tmax and Tmin, where Tmax is maximum time period of the CLOCK and Tmin is the minimum time period of the CLOCK.
Page 204: Figure 16. Ras Block Diagram
Clock & reset system RM0082 The Memory controller use the HCLK to synchronize the internal bus access and the other clock, that can be chosen from PLL1 or PLL2 (Misc register setting), is used on the external memory Interface. Two clock domains can be synchronous or asynchronous. In example we can have the CPU running at 333 MHz and the HCLK bus running at 166 MHz but having the external DDR memory running at 266 MHz to reduce the board cost.
Page 205: Figure 17. I2S Clock Schematic
RM0082 Clock & reset system Figure 17. I2S clock schematic SPEAR BISC CLOCK I2S ‘0’ DIV15-0 RAS-R-GPIO_in[40] ClkR_30MHz DIV_CPT (16bit) ClkR_Gpio4 ClkR_Gpio4 ClkR-Synt(2) bypass Isrc2-0 Internal clock RAS-R-GPIO_in[40] tck2 clock I2S_CLK TDM int_clk TDM lint_clk Invint intsel Clko0-1 Int_I2S_CLK to I2S interface Figure 18.
Page 206 Clock & reset system RM0082 With X Y/2, if the post divider is enabled (synt_clkout_sel field is cleared); while ⎛ ⎞ ∗ ⎜ ⎟ ⎝ ⎠ With X Y/2, if post divider is disable (synt_clkout_sel field is set). ⎛ ⎞ ⎜...
Page 207: Figure 19. Main Crystal Connection
RM0082 Clock & reset system It can be shown that the period drift in this case is twice the input clock period. To program the synthesizer please refer to paragraph Section 12.4.15: Auxiliary clock synthesizer registers in the Miscellaneous registers (MISC) chapter.Main oscillator 11.2.6 Crystal connection Figure 19.
Page 208: Table 155. Apb Interface Signals
Miscellaneous registers (Misc) RM0082 Miscellaneous registers (Misc) The miscellaneous block is an array of registers which manages the SoC main configuration schemes and controls all basic device functionalities; the top view is given in the next figure. Figure 21. Top view of miscellaneous registers Reg #0 Reg #1 Status...
Page 209: Table 156. Miscellaneous Register Main Memory Map
RM0082 Miscellaneous registers (Misc) 12.2 Overview features Miscellaneous register is organized in two distinct register regions: local and global register spaces. ● Local space: it's a private registers region assigned in order to ensure the right operability of the platform avoiding the register over assignment. The below region controls: –...
Page 210: Table 157. Miscellaneous Local Space Registers Overview
Miscellaneous registers (Misc) RM0082 12.4 Miscellaneous register local space 12.4.1 Overview The local register space controls the following functionalities:- ● SoC main configuration – Functional mode (up to 7 configuration are allowed): – Normal operating mode. – Debug mode: enable and control the processors embedded trace module and Embedded ICE diagnostic functionalities.
Page 211 RM0082 Miscellaneous registers (Misc) Table 157. Miscellaneous local space registers overview (continued) Misc. Local Space Register Map Base Address: 0xFCA8.0000 Region-1 Offset Region-2 Offset Register Name Type 0x0.0000 0x1.0000 PLL2_CTR 0x014 PLL2_FRQ 0x018 PLL2_MOD 0x01C PLL_CLK_CFG 0x020 CORE_CLK_CFG 0x024 PRPH_CLK_CFG 0x028 PERIP1_CLK_ENB 0x02C...
Page 212 Miscellaneous registers (Misc) RM0082 Table 157. Miscellaneous local space registers overview (continued) Misc. Local Space Register Map Base Address: 0xFCA8.0000 Region-1 Offset Region-2 Offset Register Name Type 0x0.0000 0x1.0000 ICM8_ARB_CFG 0x098 ICM9_ARB_CFG 0x09C DMA_CHN_CFG 0x0A0 USB2_PHY_CFG 0x0A4 MAC_CFG_CTR 0x0A8 Reserved 0x0AC Reserved 0x0B0...
Page 213: Table 158. Soc_Cfg_Ctr Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 157. Miscellaneous local space registers overview (continued) Misc. Local Space Register Map Base Address: 0xFCA8.0000 Region-1 Offset Region-2 Offset Register Name Type 0x0.0000 0x1.0000 SYSERR_CFG_CTR 0x11C USB0_TUN_PRM 0x120 USB_TUN_PRM 0x124 USB2_TUN_PRM 0x128 Reserved[1] 0x12C PLGPIO0_PAD_PRG 0x130 PLGPIO1_PAD_PRG 0x134...
Page 214 Miscellaneous registers (Misc) RM0082 Table 158. SoC_CFG_CTR register bit assignments (continued) SoC Functional Configuration Type 0x000 Reset Name Description Value SoC operating mode; this field reflects the Test(4:0) signal values which configure the ASIC main operating modes: Functional (ref. SoC Functional configuration type Table) Test manufacture (ref.
Page 215 RM0082 Miscellaneous registers (Misc) Table 158. SoC_CFG_CTR register bit assignments (continued) SoC Functional Configuration Type 0x000 Reset Name Description Value Same as Dyn_cfg2_0 but X01001 Dyn_cfg2_1 ARM JTAG connected with main JTAG interface Same as Dyn_cfg2_1 but ETM Interface (Single & double packet mode)
Page 216: Table 159. Diag_Cfg_Ctr Register Bit Assignments
Miscellaneous registers (Misc) RM0082 12.4.4 DIAG_CFG_CTR register The DIAG_CFG_CTR is an R/W register which configures the embedded processors ETM9 (Embedded Trace Module) and Embedded ICE-RT (TAP base debug support) diagnostic functionalities. The register bit assignments is given in the next table. Table 159.
Page 217 Reset Name Description Value SPEAr300 debug configuration (RO); this field is directly reflects the Test (1:0) signals value and it’s used to configure the internal processor Embedded ICE-RT (JTAG port) and ETM debugging features as detailed in the next table.
Page 218: Pll 1/2_Ctr Registers
Miscellaneous registers (Misc) RM0082 Table 159. DIAG_CFG_CTR register bit assignments (continued) DIAG_CFG_CTR Register 0x004 Reset Name Description Value PL_GPIO(87) ARM1_TRCSYNCB PL_GPIO(86) ARM1_PIPSTATA(0) PL_GPIO(85) ARM1_PIPSTATA(1) PL_GPIO(84) ARM1_PIPSTATA(2) PL_GPIO(83) ARM1_PIPSTATB(0) PL_GPIO(82) ARM1_PIPSTATB(1) PL_GPIO(81) ARM1_PIPSTATB(2) PL_GPIO(80) ARM1_TRCPKTA(4) PL_GPIO(79) ARM1_TRCPKTA(5) PL_GPIO(78) ARM1_TRCPKTA(6) PL_GPIO(77) ARM1_TRCPKTA(7) PL_GPIO(76) ARM1_TRCPKTB(4) PL_GPIO(75)
Page 219: Table 160. Pll 1/2_Ctr Register Bit Assignments
RM0082 Miscellaneous registers (Misc) PLL programming sequence After reset both PLLs must be firstly configured in normal mode waiting for the PLL lock valid status, than these can be optionally reconfigured in dithered mode through an additional specific programming sequence. Two different output frequency equations are provided for the above PLL operating mode: ●...
Page 220: Table 161. Pll1/2_Frq Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 160. PLL 1/2_CTR register bit assignments (continued) PLL_CTR Register 0x008 PLL2_CTR 0x014 Reset Name Description Value PLL soft reset command: [01] pll_resetn 1’h0 1’b0: PLL active reset command. 1’b1: PLL reset enable. PLL Lock Status (RO); field meaningful when PLL is configured in normal mode: [00] pll_lock...
Page 221: Pll1/2_Mod Registers
RM0082 Miscellaneous registers (Misc) Table 161. PLL1/2_FRQ register bit assignments (continued) PLL1_FRQ Register 0x00C PLL2_FRQ 0x018 Reset Name Description Value Post divider (P) table P(2:0): PLL post-divisor values in 1:32 in 2’powers (ref. Post Divider table) Pdiv2 Pdiv1 Pdiv0 Division factor [10:08] pll_postdiv_P 3’h1 N(7:0): PLL pre-divisor programmable value from 1 to 255...
Page 222: Table 162. Pll1/2_Mod Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 162. PLL1/2_MOD register bit assignments PLL1_MOD Register 0x010 PLL2_MOD 0x01C Reset Name Description Value Reserved for future use (Write don’t care - Read return [31:29] zeros). MP(12:0) PLL modulation wave parameters: Modulation rate f depends from reference clock f ref;...
Page 223: Table 163. Pll_Clk_Cfg Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 163. PLL_CLK_CFG register bit assignments PLL_CLK_CFG Register 0x020 Reset Name Description Value Reserved for future use (Write don’t care - Read return [31] zeros). MPMC memory controller DDR_CLK configuration. Synch mode: core clock provided from PLL1: 3’b000 for DDRCORE_CLK the reference frequency is HCLK.
Page 224 Miscellaneous registers (Misc) RM0082 Table 163. PLL_CLK_CFG register bit assignments (continued) PLL_CLK_CFG Register 0x020 Reset Name Description Value Main PLL1 source clock configuration table Control Description 3’b000 24 MHz Oscillator (default mode) [22:20] pll1_clk_sel 3’h0 3’b001 Programmable PL_CLK (4) signal. 3’b01X Reserved for future use.
Page 225: Table 164. Core_Clk_Cfg Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 163. PLL_CLK_CFG register bit assignments (continued) PLL_CLK_CFG Register 0x020 Reset Name Description Value Enable PLL2 clock output probing; this functionality is used to check the internal PLL2 clock integrity: [01] pll2_enb_clkout 1’h0 1’b0: Disable clock probing (normal mode). 1’b1: PLL2 clock out (clk1 x 1/8) multiplexed on basGPIO(1) signal.
Page 226: Prph_Clk_Cfg Register
Miscellaneous registers (Misc) RM0082 Table 164. CORE_CLK_CFG register bit assignments (continued) CORE_CLK_CFG Register 0x024 Reset Name Description Value PLL1_clkout to HCLK clock ratio definition (ref. next table) PLL1_clkout to HCLK configuration table Control bit Ratio Description [11:10] hclk_divsel 2’h0 2’b00 Hclk to Pll1_clkout ratio.
Page 227: Table 165. Prph_Clk_Cfg Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 165. PRPH_CLK_CFG register bit assignments PRPH_CLK_CFG Register 0x028 Reset Name Description Value Reserved for future use (Write don’t care - Read return [31:18] zeros) General purpose timer-3 clock enable [17] gptmr3_freez 1’h0 1’b0: enable clock 1;’b1: disable clock General purpose timer-2 clock enable [16]...
Page 228: Table 166. Perip1_Clk_Enb Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 165. PRPH_CLK_CFG register bit assignments (continued) PRPH_CLK_CFG Register 0x028 Reset Name Description Value Reserved for future use (Write don’t care - Read return [03:02] zeros). Enable PLL1 timer: this functionality replace PLL lock signals and it's used to control the switch transition from slow to normal operating mode when System controller PLL1 timeout event expires: 1’b0: Disable PLL1 timer functionality.
Page 229 RM0082 Miscellaneous registers (Misc) Table 166. PERIP1_CLK_ENB register bit assignments (continued) PERIP1_CLK_ENB Register 0x02C Reset Name Description Value 1’b0: Disable DDR memory controller core clock. [27] ddr_clkenb 1’h1 1’b1: Enable DDR memory controller core clock. Note: Command allowed when ddr_core_enb bit is active high. 1'b0: Used to disable USB ehci host reset.
Page 230: Table 167. Ras_Clk_Enb Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 166. PERIP1_CLK_ENB register bit assignments (continued) PERIP1_CLK_ENB Register 0x02C Reset Name Description Value 1’b0: Disable I C clock. [07] i2c_clkenb 1’h0 1’b1: Enable I C clock. [06] Reserved for future use (Write don’t care - Read return zeros). 1’b0: Disable SPI clock.
Page 231: Prsc1/2/3_Clk_Cfg Register
RM0082 Miscellaneous registers (Misc) Table 167. RAS_CLK_ENB register bit assignments (continued) RAS_CLK_ENB Register 0x034 Reset Name Description Value 1’b0: Disable internal synthesizer-4 source clock. [11] ras_synt4_clkenb 1’h0 1’b1: Enable internal synthesizer-4 source clock. 1’b0: Disable internal synthesizer-3 source clock. [10] ras_synt3_clkenb 1’h0 1’b1: Enable internal synthesizer-3 source clock.
Page 232: Table 168. Prsc1/2/3_Clk_Cfg Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 168. PRSC1/2/3_CLK_CFG register bit assignments PRSC1_CLK_CFG Register 0x044 PRSC2_CLK_CFG 0x048 PRSC3_CLK_CFG 0x04C Reset Name Description Value Reserved for future use (Write don’t care - Read return [31:16] zeros). [15:12] presc_n 4’h0 N (3:0) constant factor division value: N < 16. [11:00] presc_m 12’h0...
Page 233: Table 170. Clock Synthesizer Input Frequency
RM0082 Miscellaneous registers (Misc) Table 169. AMEM_CFG_CTRL register bit assignments (continued) AMEM_CFG_CTRL Register 0x050 Reset Name Description Value Memory port-1 source clock definition (ref. next table) Memory port2 source clock configuration table Control Bit Description 3’b000 HCLK (synchronous operating mode) (.) 3’b001 PLL1(clock synthesizer should be enable).
Page 234: Table 171. Auxiliary Clock Synthesizer Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 170. Clock Synthesizer input frequency (continued) Clock synthesizer input frequency Clock synthesizer Src. Clk1 PLL1 Src. Clk2 PLL2 Description RAS1 Clock provided from Pll1_clkout RAS2 Clock provided from Pll1_clkout Source clock selected from RAS3 ‘ras_synt34_clksel’ register field Source clock selected from RAS4 ‘ras_synt34_clksel’...
Page 235: Table 172. Perip1_Sof_Rst Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 172. PERIP1_SOF_RST register bit assignments PERIP1_SOF_RST Register 0x038 Reset Name Description Value 1’b0: Disable C3 reset. [31] C3_reset 1’h1 1’b1: Active C3 reset. [30] DDR memory controller reset enable; functionality asserted setting ‘0’ the PERIPH1_LOC_RST [27] after a previous write with PERIPH1_LOC_RST [29,27]=11: [29] ddr_core_enbr 1’h0...
Page 236: Ras_Sof_Rst Register
Miscellaneous registers (Misc) RM0082 Table 172. PERIP1_SOF_RST register bit assignments (continued) PERIP1_SOF_RST Register 0x038 Reset Name Description Value 1’b0: Disable general purpose timer-3 reset. [12] gptm3_swrst 1’h1 1’b1: Active general purpose timer-3 reset. 1’b0: Disable general purpose timer-2 reset. [11] gptm2_swrst 1’h1 1’b1: Active general purpose timer-2 reset.
Page 237: Table 173. Ras_Sof_Rst Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 173. RAS_SOF_RST register bit assignments RAS_SOF_RST Register 0x040 Reset Name Description Value [31:16 Reserved for future use (Write don’t care - Read return zeros). 1’b0: Disable reset command. [15] pl_gpck4_swrst 1’h1 1’b1: Active reset command. 1’b0: Disable reset command.
Page 238: Table 19. Basic Subsystem
Miscellaneous registers (Misc) RM0082 12.4.19 SoC configuration basic parameters 12.4.20 ICM1-8_ARB_CFG register The ICM1-8_ARB_CFG is a group of R/W registers which configure the embedded interconnection matrix arbitration protocol and the priority level of each masters; the next table shows the relations from all ICMs and their correspondent logic domains. Table 174.
Page 239 RM0082 Miscellaneous registers (Misc) Table 175. ICM 1-9_ARB_CFG register bit assignments (continued) ICM1_ARB_CFG Register 0x07C ICM2_ARB_CFG 0x080 ICM3_ARB_CFG 0x084 ICM4_ARB_CFG 0x088 ICM5_ARB_CFG 0x08C ICM6_ARB_CFG 0x090 ICM7_ARB_CFG 0x094 ICM8_ARB_CFG 0x098 Name Reset Value Description Reserved for future use (Write don’t care - Read [27:24] return zeros) mtx_fix_pry_lyr...
Page 240: Dma_Chn_Cfg Register
Miscellaneous registers (Misc) RM0082 Table 175. ICM 1-9_ARB_CFG register bit assignments (continued) ICM1_ARB_CFG Register 0x07C ICM2_ARB_CFG 0x080 ICM3_ARB_CFG 0x084 ICM4_ARB_CFG 0x088 ICM5_ARB_CFG 0x08C ICM6_ARB_CFG 0x090 ICM7_ARB_CFG 0x094 ICM8_ARB_CFG 0x098 Name Reset Value Description Master layer-0 fixed priority number level (from 0 to 7);...
Page 241: Table 176. Dma_Chn_Cfg Register Bit Assignment
RM0082 Miscellaneous registers (Misc) Table 176. DMA_CHN_CFG register bit assignment DMA_CHN_CFG Register 0x0A0 Reset Name Description Value DMA channel configuration scheme: this field configures each DMA channel assignment. Please refer to Table 588: RAS DMA configuration for the Sch_1 channel assignments.(the configuration value ‘10’...
Page 242: Table 177. Usb2_Phy_Cfg Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 177. USB2_PHY_CFG register bit assignments USB2_PHY_CFG Register 0x0A4 Name Reset Value Description [31:04] Reserved for future use. USB host over-current: enable USB controller to enter in power down state when an electrical overcurrent condition is detected on the corresponding USB bus: [03] usbh_overcur 1’h0...
Page 243: Table 179. Powerdown_Cfg_Ctr Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 178. MAC_CFG_CTR register bit assignments (continued) MAC_CFG_CTR Register 0x0A8 Name Reset Value Description Reserved for future use (Write don’t care - Read [01] return zeros) MII normal/reverse mode configuration type: 1’b0: MII normal mode (external Eth. PHY connection): both Txclk and Rxclk bidirectional signals are configured with input direction and the MII clocks are provided from the external...
Page 244: Table 180. Compsstl_1V8_Cfg/Ddr_2V5_Compensation Register Bit Assignments
Miscellaneous registers (Misc) RM0082 12.4.26 COMPSSTL_1V8_CFG/DDR_2V5_COMPENSATION register The COMPSSTL_1V8_CFG/DDR_2V5_COMPENSATION is R/W registers which configure the internal SSTL compensation cells parameters. The register bit assignments is given in the next table. Table 180. COMPSSTL_1V8_CFG/DDR_2V5_COMPENSATION register bit assignments COMPSSTL_1V8_CFG Register 0x0E4 Name Reset Value Description [31] 1’h0...
Page 245: Table 181. Compcor_3V3_Cfg Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 181. COMPCOR_3V3_CFG register bit assignments COMPCOR_3V3_CFG Register 0x0EC Name Reset Value Description [31] 1’h0 It enables IDDq mode. Writing code compensation parameter sample from the [30:24] RASRC 7'h78 compensation macro-cell during Read operating mode (ref. Compensation cell operating mode table). Reserved for future use (Write don’t care - Read return [23] zeros).
Page 246 Miscellaneous registers (Misc) RM0082 Table 182. DDR_PAD register bit assignments (continued) DDR_PAD Register 0x0F0 Reset Name Description Value It contains the value decided in the external pad DDR2_EN to select DDR (Low Power) or DDR2 (RO) [14] DDR_EN_PAD 1’b0: DDR2 1’b1: DDR Low Power Internal/External SSTL common reference voltage definition:...
Page 247: Table 183. Bist1_Cfg_Ctr Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 182. DDR_PAD register bit assignments (continued) DDR_PAD Register 0x0F0 Reset Name Description Value SSTL pad drive strength mode: the overall drive strength picture is detailed here below. 1’b0: Strong drive strength. [03] S_W_mode 1’h1 1’b1: Weak drive strength. This bit changes the output impedance of the pad.
Page 248 Miscellaneous registers (Misc) RM0082 Table 183. BIST1_CFG_CTR register bit assignments (continued) BIST1_CFG_CTR Register 0x0F4 Reset Name Description Value Memory BIST interface command: command code and BIST engine actions are detailed in the next table Memory Bist Command Table Bist command Peripherals [27] bist1-tm...
Page 249: Bist2_Cfg_Ctr Register
RM0082 Miscellaneous registers (Misc) Table 183. BIST1_CFG_CTR register bit assignments (continued) BIST1_CFG_CTR Register 0x0F4 Reset Name Description Value Run BIST execution command (ref. Memory BIST command): 1’b0: Disable BIST command 15’h0 1’b1: Run BIST command: memory BIST execution can be done either in single or group mode (ref.
Page 250: Table 184. Bist2_Cfg_Ctr Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 184. BIST2_CFG_CTR register bit assignments BIST2_CFG_CTR Register 0x0F8 Reset Name Description Value Reset status register result (BIST2_STS_RES) [31] bist2_res_rst 1’h0 1’b0: Disable reset 1’b1: Active reset Reserved for future use (Write don’t care - Read return [30:29] zeros).
Page 251: Table 185. Bist3_Cfg_Ctr Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 185. BIST3_CFG_CTR register bit assignments BIST3_CFG_CTR Register 0x0FC Name Reset Value Description Reset status register result (BIST3_STS_RES) [31] bist3_res_rst 1’h0 1’b0: Disable reset 1’b1: Active reset. Reserved for future use (Write don’t care - Read [30:29] return zeros).
Page 252: Table 186. Bist4_Cfg_Ctr Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 186. BIST4_CFG_CTR register bit assignments BIST4_CFG_CTR Register 0x100 Name Reset Value Description Reset status register result (BIST4_STS_RES): [31] bist4_res_rst 1’h0 1’b0: Disable reset 1’b1: Active reset Reserved for future use (Write don’t care - Read return [30:29] zeros).
Page 253: Table 187. Bist1_Sts_Res Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 187. BIST1_STS_RES register bit assignments BIST1_STS_RES Register 0x108 Reset Name Description Value End memory BIST 1 execution: [31] bist1_end 1’b0: BIST execution pending. 1’b1: End memory BIST execution. [30:24] Reserved for future use (Write don’t care - Read return zeros). [23:15] Reserved for BIST bad extension field.
Page 254: Table 188. Bist2_Sts_Res Register Bit Assignments
Miscellaneous registers (Misc) RM0082 12.4.35 BIST2_STS_RES register The BIST2_STS_RES in an RO register which returns the functional BIST execution results for the RAS-1 memory sub-group. The register bit assignments is given in the next table. Table 188. BIST2_STS_RES register bit assignments BIST2_STS_RES Register 0x10C Reset...
Page 255: Bist3_Sts_Res Register
RM0082 Miscellaneous registers (Misc) Table 188. BIST2_STS_RES register bit assignments (continued) BIST2_STS_RES Register 0x10C Reset Name Description Value BIST execution result (BIST bad signal status): 1’b0: BIST execution ok. 1’b1: BIST execution fails (ref. next table) Bist failure table Bbad Memory Cut Peripherals ST_SPREG_2048...
Page 256: Table 189. Bist3_Sts_Res Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 189. BIST3_STS_RES register bit assignments BIST3_STS_RES Register 0x110 Reset Name Description Value End memory BIST3 execution: [31] bist3_end 1’b0: BIST execution pending 1’b1: End memory BIST execution. Reserved for future use (Write don’t care - Read return [30:14] zeros).
Page 257: Table 190. Bist4_Sts_Res Register Bit Assignments
RM0082 Miscellaneous registers (Misc) 12.4.37 BIST4_STS_RES register The BIST4_STS_RES is an RO register which returns the functional BIST execution results for the ARM internal memory pool. The register bit assignments is given in the next table Table 190. BIST4_STS_RES register bit assignments BIST4_STS_RES Register 0x114 Reset...
Page 258: Bist5_Rslt_Reg Register (Reserved)
Miscellaneous registers (Misc) RM0082 Table 190. BIST4_STS_RES register bit assignments (continued) BIST4_STS_RES Register 0x114 Reset Name Description Value BIST execution result (BIST bad signal status): 1’b0: BIST execution ok 1’b1: BIST execution fails (ref. next table) Bist failure table Bbad Memory Cut Peripherals ARM_SPREG_1024x3...
Page 259: Table 191. Bist5_Rslt_Reg Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 191. BIST5_RSLT_REG register bit assignments BIST5_RSLT_REG Register 0x118 Reset Name Description Value end memory BIST5 execution: [31] bist5_end 1’b0: BIST execution pending 1’b1: end memory BIST execution. [30:24] reserved for future use (write don’t care - read return zeros). [23:20] reserved for BIST bad extension field BIST execution result (BIST bad signal status):...
Page 260: Table 192. Syserr_Cfg_Ctr Register Bit Assignments
Miscellaneous registers (Misc) RM0082 12.4.39 Diagnostic functionality 12.4.40 SYSERR_CFG_CTR register The SYSERR_CFG_CTR is an R/W register which configures the SoC internal error detections. The register bit assignments is detailed in the next table. Table 192. SYSERR_CFG_CTR register bit assignments SYSERR_CFG_CTR Register 0x11C Reset Name...
Page 261 RM0082 Miscellaneous registers (Misc) Table 192. SYSERR_CFG_CTR register bit assignments (continued) SYSERR_CFG_CTR Register 0x11C Reset Name Description Value Reserved for future use (Write don’t care - Read return [21:16] zeros). [15] mem_dll_err 1’h0 PLL/DLL unlock error (RO); detection enable through 'pll_err_enb' register field set high: [14] usb_pll_err...
Page 262: Table 193. Usb_Tun_Prm Register Bit Assignments
Miscellaneous registers (Misc) RM0082 12.4.41 USB_TUN_PRM register To enable adjusting various USB 2.0 specification-related characteristics, the USB 2.0 nanoPHY provides top level parameter override bits. The USB 2.0 nanoPHY is designed to a default setting of these bits, and you are not expected to have to change these bits from their default setting.
Page 263: Table 195. Pull Up And Pull Down Selection
RM0082 Miscellaneous registers (Misc) Table 195. Pull Up and Pull Down Selection Comment Not Allowed Pull-Up Activated Pull-Down Activated Pull-Up/Pull-Down deactivated Table 196. Slew selection Slew level Nominal Fast In general for programming purposes the slew and drive strength of Four pads are shared by a bit as specified in table below with some exception as specified in the table.
Page 264: Table 198. Plgpio1_Pad_Prg Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 197. PLGPIO0_PAD_PRG register bit assignments (continued) PLGPIO0_PAD_PRG 0x130 Name Reset Value Description [08] PUP_1 1’h0 Pull up control for pads 6,7 [07:06] DRV_1[1:0] 2’h0 Drive strength control for pads 4,5,6,7 [05] SLEW_1 1’h0 Slew control for pads 4,5,6,7 [04] PDN_0 1’h1...
Page 265: Table 199. Plgpio2_Pad_Prg Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 198. PLGPIO1_PAD_PRG register bit assignments (continued) PLGPIO1_PAD_PRG 0x134 Name Reset Value Description [04] PDN_6 1’h1 Pull down control for pads 24,25,26,27 [03] PUP_6 1’h0 Pull Up control for pads 24,25,26,27 [02:01] DRV_6[1:0] 2’h0 Drive Strength control for pads 24,25,26,27 [00] SLEW_6 1’h0...
Page 266: Table 200. Plgpio3_Pad_Prg Register Bit Assignments
Miscellaneous registers (Misc) RM0082 Table 199. PLGPIO2_PAD_PRG register bit assignments PLGPIO2_PAD_PRG 0x138 Reset Name Description Value [02:01] DRV_12[1:0] 2’h0 Drive Strength control for pads48,49,50,51 [00] SLEW_12 1’h0 Slew control for pads 48,49,50,51 Table 200. PLGPIO3_PAD_PRG register bit assignments PLGPIO3_PAD_PRG 0x13C Reset Name Description...
Page 267: Table 201. Plgpio4_Pad_Prg Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 201. PLGPIO4_PAD_PRG register bit assignments PLGPIO4_PAD_PRG 0x140 Reset Name Description Value [31:25] Reserved for future use (Read return zeros) [24] PDN_CLK4 1’h1 Pull down control for pads CLK4 [23] PUP_CLK4 1’h0 Pull up control for pads CLK4 [22:21] DRV_CLK4[1:0] 2’h0...
Page 268: Table 202. Miscellaneous Global Space Registers Overview
Miscellaneous registers (Misc) RM0082 12.5.2 Miscellaneous register global space address map Next table shows the miscellaneous global register map. Table 202. Miscellaneous global space registers overview Miscellaneous Global Space Register Map Base Address: 0xFCA8.0000 Alias-1 Offset Alias-2 Offset Register Name Type 0x0.8000 0x1.8000...
Page 269: Table 205. Ras_Gpp_Ext_In Register Bit Assignments
RM0082 Miscellaneous registers (Misc) Table 205. RAS_GPP_EXT_IN register bit assignments RAS_GPP_EXT_IN Register 0x010 Reset Name Description Value General purpose input register (RO) which return [07:00] Gpp_ext_in[07:00] the current value of the programmable logic signals. 12.5.4 RAS1/2_GPP_OUT register The RAS1/2_GPP_OUT are a group of R/W general purpose output registers used to pass different kind of data/command from the internal core logic to reconfigurable logic array.
Page 270: Figure 22. Spi Block Diagram
LS_Synchronous serial peripheral (SSP) RM0082 LS_Synchronous serial peripheral (SSP) 13.1 Overview Within its low speed connectivity, the device provides one ARM PrimeCell® synchronous serial port (SSP) block that offers a master or slave interface to enables synchronous serial communication with slave or master peripherals Main features of the SSP are: ●...
Page 271: Table 209. Ssp Signal Interface
RM0082 LS_Synchronous serial peripheral (SSP) 13.3 Signal interfaces The SSP directly interfaces with the signals summarized in Table 209 Table 209. SSP signal interface Group Signal name Direction Size (bit) Description Input Main SSP clock input. Global nRST Input SSP reset signal. TXINTR Output Transmit FIFO service request interrupt.
Page 272: Register Block
LS_Synchronous serial peripheral (SSP) RM0082 hierarchy. The AMBA APB groups narrow-bus peripherals to avoid loading the system bus and provides an interface using memory-mapped registers, which are accessed under programmed control. 13.4.2 Register block The register block stores data written or to be read across the AMBA APB interface. 13.4.3 Clock prescaler When configured as a master, an internal prescaler, comprising two free-running re-...
Page 273: Interrupt Generation Logic
RM0082 LS_Synchronous serial peripheral (SSP) parallel to serial conversion, then output the serial data stream and frame control signal through the slave SSPTXD pin. The slave receive logic performs serial to parallel conversion on the incoming SSPRXD data stream, extracting and storing values into its receive FIFO, for subsequent reading through the APB interface.
Page 274: Table 210. External Cs Selection
LS_Synchronous serial peripheral (SSP) RM0082 Control registers SSPCR0 and SSPCR1 need to be programmed to configure the peripheral as a master or slave operating under one of the following protocols: ● Motorola SPI ● Texas Instruments SSI ● National Semiconductor. The bit rate, derived from the APB clock (PCLK), requires the programming of the clock prescale register SSPCPSR.
Page 275: Programming The Sspcr0 Control Register
RM0082 LS_Synchronous serial peripheral (SSP) To generate a maximum bit rate of 1.8432 Mbps in the Master mode, the frequency of SSPCLK must be at least 3.6864 MHz. With an SSPCLK frequency of 3.6864 MHz, the SSPCPSR register has to be programmed with a value of two and the SCR[7:0] field in the SSPCR0 register needs to be programmed as zero.
Page 276: Frame Format
LS_Synchronous serial peripheral (SSP) RM0082 To enable the operation of the PrimeCell SSP set the Synchronous Serial Port Enable (SSE) bit to 1. Bit rate generation Dividing down the input clock SSPCLK derives the serial bit rate. The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in SSPCPSR.
Page 277: Table 211. External Pin Connection
RM0082 LS_Synchronous serial peripheral (SSP) 13.6 Programming model 13.6.1 External pin connections Table 211. External pin connection Signal Ball MOSI MISO 13.6.2 Register map The SSP can be fully configured by programming its registers which can be accessed through the APB slave interface at the following base address: Table 212.
Page 278: Table 213. Sspcr0 Register Bit Assignments
LS_Synchronous serial peripheral (SSP) RM0082 Table 212. SSP registers summary (continued) Width Reset Name Offset Type Description (bit) value SSPCellID0 0xFF0 RO 8’hD PrimeCell identification register bits 7:0 SSPCellID1 0xFF4 RO 8’hF0 PrimeCell identification register bits 15:8 SSPCellID2 0xFF8 RO 8’h5 PrimeCell identification register bits 23:16 SSPCellID3...
Page 279: Table 214. Sspcr1 Register Bit Assignments
RM0082 LS_Synchronous serial peripheral (SSP) 13.6.5 SSPCR1 register SSPCR1 is the control register 1 and contains four different bit fields, which control various functions within the SSP. Table 214. SSPCR1 register bit assignments Name Type Description [15:04] - Reserved. Read unpredictable, should be written as 0 Slave-mode output disable.
Page 280: Table 215. Sspdr Register Bit Assignments
LS_Synchronous serial peripheral (SSP) RM0082 Table 215. SSPDR register bit assignments Name Type Description Transmit/receive FIFO: Read = Receive FIFO Write = Transmit FIFO [15:00] DATA You must right justify data when the SSP is programmed for a data size that is less then 16 bits.
Page 281: Table 217. Sspcpsr Register Bit Assignments
RM0082 LS_Synchronous serial peripheral (SSP) Table 217. SSPCPSR register bit assignments Name Type Description [15:08] - Reserved, read unpredictable, must be written as 0. Clock prescale divisor. Must be an even number from 2 to 254, [07:00] CPSDVSR R/W depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.
Page 282: Table 220. Sspmis Register Bit Assignments
LS_Synchronous serial peripheral (SSP) RM0082 Table 219. SSPRIS register bit assignments (continued) Name Type Description Gives the raw interrupt state (prior to masking) of the SSPRXINTR [02] RXRIS interrupt Gives the raw interrupt state (prior to masking) of the SSPRTINTR [01] RTRIS interrupt...
Page 283: Table 222. Sspdmacr Register Bit Assignments
RM0082 LS_Synchronous serial peripheral (SSP) Table 222. SSPDMACR register bit assignments Name Type Description [15:02] Reserved, read as 0, do not modify. [01] TXDMAEn If this bit is set to 1, DMA for the transmit FIFO is enabled. [00] RXDMAEn If this bit is set to 1, DMA for the receive FIFO is enabled.
Page 284: Table 227. Pcellid0 Register Bit Assignments
LS_Synchronous serial peripheral (SSP) RM0082 13.6.18 PCELLID0 register Table 227. PCELLID0 register bit assignments Name Type Description [31:08] Reserved, read as zero [07:00] PCELLID0 These bits read back as 0x0D 13.6.19 PCELLID1 register Table 228. PCELLID1 register bit assignment Name Type Description [31:08]...
Page 285: Ssprxintr
RM0082 LS_Synchronous serial peripheral (SSP) Provision of the individual outputs as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts SSPTXINTR and SSPRXINTR have been separated from the status interrupts, so that data can be read or written in response to just the FIFO trigger levels.
Page 286: Overview
BS_System controller RM0082 BS_System controller 14.1 Overview Within its Basic Subsystem, the device provides a System Controller, which is used to supply an interface to control the operation of the overall system. Main features of the System Controller are listed below: ●...
Page 287: Figure 23. System Controller Block Diagram
RM0082 BS_System controller 14.2 Block diagram Figure 23. System controller block diagram Clock and reset nPOR inputs SCLK PRESETn PENABLE PSEL PRDATA[31:0] APB interface PWRITE PWDATA[31:0] PADDR[11:2] PLLON PLLEN PLL oscillator PLLSW PLLRQSW control and status PLLTIMEEN PLLFREQCTRL[31:0] XTALON XTALEN Crystal oscillator XTALSW XTALRQSW...
Page 288 BS_System controller RM0082 The state machine is controlled using three mode control bits (ModeCtrl[2:0]) in the system control register (SCCTRL), which define the required system operating mode. The mode control bits control the modes: ● 1xx If the most significant bit (MSB) is set then the system moves into NORMAL mode. ●...
Page 289 RM0082 BS_System controller XTAL control transition state, XTAL CTL XTAL control transition state is used to initialize the crystal oscillator. While in this state, both the system clocks and the System Controller clock are driven from a low-frequency oscillator. The system moves into the Switch to XTAL transition state when the crystal oscillator output is stable.
Page 290: Figure 24. System Mode Control State Machine
BS_System controller RM0082 14.3.2 System control state machine Figure 24. System mode control state machine NORMAL PLLSW NORMAL SW to SW From PLLON ||(PLLTIMEEN && PLL Timeout) PLL SW NORMAL SLOW XTAL SW SLOW&NORMAL SW to XTAL XTALON ||(XTALTIMEEN && XTAL Timeout) SW From XTAL XTAL...
Page 291: Interrupt Response Mode
RM0082 BS_System controller 14.3.3 Interrupt response mode To enable the best possible response to interrupts, the present mode bits can be override in the system control register after an interrupt has been generated. This enables, for example, the state machine to move from the DOZE to the NORMAL mode after an interrupt. The interrupt response functionality is controlled by the interrupt mode control register (SCIMCTRL, Section...
Page 292: Table 231. System Controller Control And Status Registers Summary
BS_System controller RM0082 14.4 Programming model 14.4.1 Register map The system controller can be fully configured by programming its registers which can be accessed at the base address 0xFCA0_0000 System controller registers can be logically arranged in two main groups: ●...
Page 293: Table 233. Scctrl Register Bit Assignments
RM0082 BS_System controller Table 232. System controller identification registers summary (continued) Name Offset Width[bit] Type Reset Value Description SCPeriphID0 0xFE0 8’h10 SCPeriphID1 0xFE4 8’h18 Peripheral identification SCPeriphID2 0xFE8 8’h04 SCPeriphID3 0xFEC 8’h00 SCPCellID0 0xFF0 8’h0D SCPCellID1 0xFF4 8’hF0 Identification Registes SCPCellID2 0xFF8 8’h05...
Page 294: Scsysstat Register
BS_System controller RM0082 Table 233. SCCTRL register bit assignments (continued) Reset Name Description value [15] TimerEn0Sel 1’h0 Timer enable 0, timing reference select [14:12] HCLKDivSel 3’h0 Control the HCLKDIVSEL output [11:10] Reserved Read: undefined. Write: should be zero Remap status [09] RemapStat 1’h0...
Page 295: Table 234. Scimctrl Register Bit Assignments
RM0082 BS_System controller 14.4.5 SCIMCTRL register The SCIMCTRL (interrupt mode control) is a RW register which is used to enable and control the operation of the system controller when an interrupt has been generated. The SCIMCTRL bit assignments are given in Table 234.
Page 296: Table 236. Scxtalctrl Register Bit Assignments
BS_System controller RM0082 14.4.7 SCXTALCTRL register The SCXTALCTRL (crystal control) is a RW register which is used to directly control the crystal oscillator used to generate the system clock SCLK in both SLOW and NORMAL mode (Section 14.3.1: System mode control).
Page 297 RM0082 BS_System controller Table 237. SCPLLCTRL register bit assignments (continued) Reset Name Type Description value PLL status bit [02] PllStat 1’h0 This RO bit returns the value on the PLLON input signal. PLL enable bit This bit is used to directly control the PLLEN [01] PllEn 1’h0...
Page 298: Overview
15.1 Overview SPEAr300 provides a serial memory interface (SMI), acting as an AHB slave interface (32, 16 or 8 bit) to SPI-compatible off-chip memories. SMI allows the CPU to use these serial memories for both data storage and code execution.
Page 299: Figure 25. Smi Block Diagram
RM0082 BS_Serial memory interface Figure 25. SMI block diagram Clock SMI Clock Prescaler (1 to 127) Data, command SMI Data processing Bank select and Control SPI- Transmit Register Compatible Memories AHB Slave Control and Interface Status Register Receive Register/ Status Regsiter Data, Status 15.3...
Page 300: Table 238. Smi Supported Instruction
BS_Serial memory interface RM0082 Note: If EEPROMs are used instead of Flash memories, a read request address should be (ADDRESS + 1), being ADDRESS the actual target address to be read. ● Write requests: wrapping bursts are not supported, causing an ERROR response on HRESP sent back by SMI to AHB master.
Page 301: Figure 26. External Spi Memory Map In Ahb Address Space
RM0082 BS_Serial memory interface In particular, external serial memory is mapped in AHB address space as shown in Figure Figure 26. External SPI memory map in AHB address space 0xF9FF_FFFF 0xF9FF_FFFF 0xF900_0000 External Serial M em ory Space 0xF8FF_FFFF 0xF800_0000 0xF800_0000 In this mode, both the transmit register SMI_TR (Section...
Page 302: Write Request
BS_Serial memory interface RM0082 When a read request occurs in normal mode (that is, frequency up to 20 MHz), the SMI sends the following data sequence to the bank selected by the AHB address bits [24.25]. ● Read data bytes instruction opcode (8’h03) ●...
Page 303: Write Burst Mode
RM0082 BS_Serial memory interface After a Write request has been sent, the WM bit in SMI_SR register is cleared and the read status register instruction (opcode 8’h05, Table 238) is automatically sent to this bank until no write in progress (WIP =1‘b0). Note: Write capability must be used only if write in progress / busy bit of the external memory status register is located in bit 0.
Page 304: Erase And Write Status Register
BS_Serial memory interface RM0082 15.5.5 Erase and write status register In case of serial Flash, an erase may be necessary before writing. Due to incompatibility between different serial Flash vendors, erase and write status register can be done only in software mode.
Page 305: How To Boot From External Memory
RM0082 BS_Serial memory interface ) for a byte, because of no mandatory extra commands (instruction opcode and SMI_CK address). Moreover, for AHB write burst transfers, the maximum latency for the 2 transfer is (data size + opcode + address bytes) whereas, it is the same as data size for following transfers.
Page 306: Table 239. External Pin Connection
BS_Serial memory interface RM0082 15.8 Programming model 15.8.1 External pin connection Table 239. External pin connection Signal Ball SMI_DATAIN SMI_DATAOUT SMI_CLK SMI_CS_0 SMI_CS_1 The SMI can be fully configured by programming a set of 32 bit wide registers (listed in Table 240) which can be accessed at the base address 0xFC00_0000 Note:...
Page 307 RM0082 BS_Serial memory interface Table 241. SMI_CR1 register bit assignments (continued) Reset Name Type Description value Software mode. Setting this bit, the software operation mode of SMI is [28] 1’h0 enabled (Section 15.4), otherwise (bit cleared, default), the hardware operation mode is enabled. Address length.
Page 308: Table 242. Smi_Cr2 Register Bit Assignments
BS_Serial memory interface RM0082 Table 241. SMI_CR1 register bit assignments (continued) Reset Name Type Description value [03:02] Not used Bank enable. This is a 2 bit field where each bit is associated to a specific external memory bank, specifically the LSB (bit [0]) refers to bank0.
Page 309: Smi_Sr Register
RM0082 BS_Serial memory interface Table 242. SMI_CR2 register bit assignments (continued) Reset Name Type Description value Read status register command. Setting this bit, a read status register command is sent to the memory bank selected by the BS field. Result from memory is then loaded into the SMSR field of SMI_SR [10] 1’h0...
Page 310: Table 243. Smi_Sr Register Bit Assignments
BS_Serial memory interface RM0082 Table 243. SMI_SR register bit assignments Reset Name Type Description value [31:16] Reserved Read: undefined. Write mode for selected bank. This 2 bit field report the write mode (Section 15.5.2) status for the four supported memory banks. Each bit is associated to a single bank (specifically the LSB, bit [12], refers to [15:14] 2’h0...
Page 311: Table 244. Smi_Tr Register Bit Assignments
RM0082 BS_Serial memory interface Table 243. SMI_SR register bit assignments (continued) Reset Name Type Description value Transfer finished flag. This bit is set when transfer with external memory is completed, that is after REC_LENGTH and TRA_LENGTH bytes (set in SMI_CR2 register, Section 15.8.4) have been [08]...
Page 312: Table 245. Smi_Rr Register Bit Assignments
BS_Serial memory interface RM0082 This register must be read in software mode (bit SW set in SMI_CR1 register, Section 15.8.3) after transfer is finished (bit TFF set in SMI_SR register, Table 243), otherwise the register content is not valid. Note: The SMI_RR is also used in Hardware mode, but its content is not kept entering in this mode.
Page 313: Figure 27. Watchdog Module Block Diagram
RM0082 BS_Watchdog timer BS_Watchdog timer 16.1 Overview Within its basic subsystem, the device provides an ARM watchdog module. It consists of a 32 bit down counter with a programmable time-out interval that has the capability to generate an interrupt and a reset signal on timing out. The watchdog module is intended to be used to apply a reset to a system in the event of a software failure.
Page 314: Table 246. Watchdog Module Counter Decremented
BS_Watchdog timer RM0082 16.3 Main functions description 16.3.1 AMBA APB interface The AMBA APB interface block provides an APB slave which allows to accesses to all registers in the watchdog module. In particular, the lock register (WdogLock, Section 16.5.9) controls the enabling of write accesses to all the other registers in order to ensure software cannot unintentionally disable the watchdog module operation.
Page 315: Table 247. Watchdog Control And Status Registers Summary
RM0082 BS_Watchdog timer 16.5 Programming model 16.5.1 Register map The watchdog module can be fully configured by programming its 32 bit wide registers which can be accessed at the base address 0xFC88_0000. Watchdog registers can be logically arranged in two main groups: ●...
Page 316: Table 249. Wdogcontrol Register Bit Assignments
BS_Watchdog timer RM0082 16.5.2 Register description 16.5.3 WdogLoad register The WdogLoad is a RW register that contains the value from which the counter is to decrement. When this register is written to, the counter is immediately restarted from the new value. The minimum valid value for WdogLoad is 32’h1. Note: If WdogLoad is set to 32’h0 then an interrupt is generated immediately.
Page 317: Table 250. Wdogris Register Bit Assignments
RM0082 BS_Watchdog timer 16.5.7 WdogRIS register The WdogRIS (raw interrupt status) is a RO register indicates the raw interrupt status from the counter (before masking by WdogControl register). The WdogRIS bit assignments are given in Table 250. Table 250. WdogRIS register bit assignments Name Reset value Description...
Page 318: Table 253. External Pin Connection
8 bit timer clock prescaler. The programmable 8 bit prescaler performs a clock division by 1 up to 256, and different input frequencies can be chosen through SPEAr300 configuration registers (so we can synthesize, for instance, a frequency range from 3.96 Hz to 48 MHz).
Page 319: Figure 28. Gpt Block Diagram
RM0082 BS_General purpose timers Table 253. External pin connection (continued) Subsystem Basic address Signals Ball Usage Note TMR_CL Output signal which toggles TIMER generates an interrupt. (OUTPUT generated for both TMR_CL TIMER/CAPTURE MODE) 0xFC80_0000 TMR_CP These Input pins are used to receive the signals for which the measurement of timing is TMR_CP...
Page 320: Table 254. Gpt Interface Signal Description
BS_General purpose timers RM0082 Table 254. GPT interface signal description Pin Name Type Source/Destination Description APB system (bus) clock. This clock times all the bus transfers. Clock root Synchronous logic inside the GPT id rising edge clock triggered. Synchronous reset of the GPT, all RESETn Reset block internal registers are cleared when this...
Page 321: Table 255. Couple Of Gpts Registers Summary
RM0082 BS_General purpose timers Table 255. Couple of GPTs registers summary Reset Name Offset Type Description Value Control register of 1 timer in the TIMER_CONTROL1 0x0080 16’h0000 couple (GPT0 or GPT2). TIMER_STATUS_INT_ACK1 0x0084 16’h0000 Status register of 1 timer. TIMER_COMPARE1 0x0088 16’hFFFF Compare register of 1...
Page 322: Table 257. Prescaler Configuration
BS_General purpose timers RM0082 Table 256. Timer_Control register bit assignments (continued) Name Reset value Description Timer enable. Setting this bit, the GPT is enabled. Once enabled, an initialization phase is performed before starting to count, and capture registers (TIMER_REDG_CAPT and [05] ENABLE 1’h0...
Page 323: Table 258. Timer_Status_Int_Ack Register Bit Assignments
RM0082 BS_General purpose timers Table 258. TIMER_STATUS_INT_ACK register bit assignments Name Reset value Description [15:03] Reserved 13’h0 Read undefined. Write: should be zero. Rising edge capture. Reading this bit as 1‘b1, it means that a rising edge has been detected on the capture input and an interrupt is [02] REDGE 1’h0...
Page 324: Table 260. Timer_Count Register Bit Assignments
BS_General purpose timers RM0082 17.2.7 TIMER_COUNT register The TIMER_COUNT is a RO register indicates the current counter value. The TIMER_COUNT bit assignments are given in Table 260. Table 260. TIMER_COUNT register bit assignments Name Reset value Description [15:00] CONT_VALUE 16’h0000 Current counter value.
Page 325: Table 263. Gpio Signal Interface
BS_General purpose input/output (GPIO) BS_General purpose input/output (GPIO) 18.1 Overview Within its Basic Subsystem, SPEAr300 provides a General Purpose Input/Output (GPIO) providing 6 programmable inputs or outputs. Each input/output can be controlled through an APB interface. Main features of the GPIO are: ●...
Page 326: Figure 30. Gpio Signal Interfaces Diagram
BS_General purpose input/output (GPIO) RM0082 Table 263. GPIO signal interface (continued) Size Group Signal name Direction Description (bit) Masked interrupt signals, to interrupt GPIOMIS Output controller. Interrupt (on-chip) Combined OR version of GPIOMIS, to GPIOINTR Output interrupt controller. APB Slave Input/Output - See AMBA specification.
Page 327: Mode Control
RM0082 BS_General purpose input/output (GPIO) 18.3.3 Mode control Each GPIO line can be controlled through APB interface. The data direction is controlled by the data direction register (GPIODIR, Section 18.5.3). Data writing and reading are performed through APB interface, according to operation detailed in Section 18.4.
Page 328: Figure 31. Gpio Interrupt Triggering Logic
BS_General purpose input/output (GPIO) RM0082 Figure 31. GPIO interrupt triggering logic Start GPIOIE Interrupt Masked? masked GPIOIS Edge/level? GPIOIBE both edges? GPIOIEV GPIOIEV HIGH/LOW? Rising/falling? Note: For level detection case, it is assumed that an external source holds the level constant for the interrupt to be recognized by the processor.
Page 329: Table 264. Gpio Data Direction Register
RM0082 BS_General purpose input/output (GPIO) Note: The same data register appears at 64 locations in Memory Map (with offset ranging from 0x00 to 0xFC), allowing to use the address bus [9:2] as an additional bit masking feature. ● Interrupt Control Registers (listed in Table 266), for interrupt generation configuration.
Page 330: Table 268. Gpiodir Register Bit Assignments
BS_General purpose input/output (GPIO) RM0082 18.5.2 Register description 18.5.3 GPIODIR register The GPIODIR is the data direction RW register which allows to configure each pin as either an input or an output. The GPIODIR bit assignments are given in Table 268.
Page 331: Table 271. Gpioibe Register Bit Assignments
RM0082 BS_General purpose input/output (GPIO) 18.5.6 GPIOIBE register The GPIOIBE (Interrupt Both Edges) is a RW register which allows to configure each pin to detect both rising and falling edges for interrupt triggering, in case edge detection for that pin is enabled (clearing relevant bit in GPIOIS register).
Page 332: Table 274. Gpioris Register Bit Assignments
BS_General purpose input/output (GPIO) RM0082 18.5.9 GPIORIS register The GPIORIS (Raw Interrupt Status) is a RO register which reflects the raw status (prior to masking through GPIOIE register) of interrupts trigger conditions on each pin. The GPIORIS bit assignments are given in Table 274.
Page 333: Overview
BS_DMA controller BS_DMA controller 19.1 Overview Within its basic subsystem, SPEAr300 provides an DMA controller (DMAC) able to service up to 8 independent DMA channels for sequential data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral).
Page 334: Figure 32. Dmac Block Diagram
BS_DMA controller RM0082 19.2 Block diagram Figure 32. DMAC block diagram AHB MASTER DMACCLR[15:0] DMACTC[15:0] MAST CHANNEL 0 DMACSREQ[15:0] REQUEST DMACBREQ[15:0] RESPONSE DMACLSREQ[15:0] BLOCK DMACLBREQ[15:0] AHB MASTER 2 MAST CHANNEL 1 AHB SLAVE INTERFACE CHANNEL 7 19.3 Signal interfaces The DMAC directly interfaces with the signals summarized in Table 277.
Page 335: Table 277. Dmac Signal Interface
RM0082 BS_DMA controller Table 277. DMAC signal interface Size Group Signal name Direction Description (bit) DMACBREQ Input DMA burst transfer request. DMACLBREQ Input DMA last burst transfer request. DMA request DMACSREQ Input DMA single transfer request. DMACLSREQ Input DMA last single transfer request DMACCLR Output DMA request clear.
Page 336: Dma Interface
BS_DMA controller RM0082 width or narrower than the physical bus width. In this case, the DMAC packs or unpacks data as appropriate. Note: The DMAC uses HSIZE1 or HSIZE2 to indicate the width of a transfer, and if this fails to match the width expected by the peripheral, then the peripheral can assert an error on HRESP1 or HRESP2, respectively.
Page 337: Figure 34. Dmac-To-Interrupt Controller Connection
RM0082 BS_DMA controller Note: The DMAC configuration is not part of the LLI description, but allows to configure the relevant DMA channel. 19.5.1 How to program the DMAC for scatter/gather DMA Write to memory all the LLIs for the complete DMA transfer (source address, destination address, pointer to next LLI and control word for each LLI).
Page 338: Table 278. Dmac Global Registers Summary
BS_DMA controller RM0082 19.6.1 How to operate single combined DMACINTR interrupt request signal Wait until the combined interrupt request from the DMAC (DMACINTR) goes active. Read the interrupt controller status register and determine whether the source of the request was the DMAC. Read the DMACIntStatus register (Section 19.7.4) to determine the DMA channel that...
Page 339: Table 279. Dmac Channel Registers Summary
RM0082 BS_DMA controller Table 278. DMAC global registers summary (continued) Reset Name Offset Type Description Value DMACEnbldChns 0x01C 32’h0 Enabled channel. DMACSoftBReq 0x020 32’h0 Software burst request. DMACSoftSReq 0x024 32’h0 Software single request. DMACSoftLBReq 0x028 32’h0 Software last burst request. DMACSoftLSReq 0x02C 32’h0...
Page 340: Table 282. Dmacintstatus Register Bit Assignments
BS_DMA controller RM0082 19.7.2 Register description 19.7.3 DMACIntStatus register The DMACIntStatus (interrupt status) is a RO register which shows the status of the interrupts after masking. The DMACIntStatus bit assignments are given in Table 282. Table 282. DMACIntStatus register bit assignments Name Reset value Description [31:08]...
Page 341: Table 284. Dmacinttcclear Register Bit Assignments
RM0082 BS_DMA controller Table 284. DMACIntTCClear register bit assignments Name Reset value Description [31:08] Reserved Write as zero. Terminal count request clear. Each bit is associated to a DMA channel. When writing to this register, each bit that is set causes the corresponding bit [07:00] IntTCClear 8’h00 in the DMACIntTCStatus register to be cleared.
Page 342: Table 287. Dmacrawinttcstatus Register Bit Assignments
BS_DMA controller RM0082 19.7.8 DMACRawIntTCStatus register The DMACRawIntTCStatus (raw interrupt terminal count status) is a RO register which indicates the DMA channels that are requesting a transfer complete, terminal count interrupt, prior to masking. The DMACRawIntTCStatus bit assignments are given in Table 287.
Page 343: Table 290. Dmacsoftbreq Register Bit Assignments
RM0082 BS_DMA controller 19.7.11 DMACSoftBReq register The DMACSoftBReq (software burst request) is a RW register which enables DMA burst requests to be generated by software. The DMACSoftBReq bit assignments are given in Table 290. Table 290. DMACSoftBReq register bit assignments Name Reset value Description...
Page 344: Table 292. Dmacsoftlbreq Register Bit Assignments
BS_DMA controller RM0082 Table 292. DMACSoftLBReq register bit assignments Name Reset value Description [31:16] Reserved Read: undefined. Write as zero. Software last burst request. Each bit is associated to one out of 16 peripheral DMA request lines. Setting a bit, a DMA last burst request for the [15:00] SoftLBReq 16’h0000...
Page 345: Table 295. Dmacsync Register Bit Assignments
RM0082 BS_DMA controller Table 294. DMACConfiguration register bit assignments (continued) Name Reset value Description AHB master 1 endianness configuration. This bit enables to alter the endianness of the AHB master [01] 1’h0 interface 1, according to the same encoding as M2 (see above).
Page 346: Table 296. Dmaccnsrcaddr Register Bit Assignments
BS_DMA controller RM0082 Table 296. DMACCnSrcAddr register bit assignments Name Reset value Description [31:00] SrcAddr 32’h0 DMA source address. 19.7.18 DMACCnDestAddr register The DMACCnDestAddr (channel n destination address) is a RW register which contains the current destination address (byte-aligned) of the data to be transferred over the n-th DMA channel.
Page 347: Table 299. Dmaccncontrol Register Bit Assignments
RM0082 BS_DMA controller 19.7.20 DMACCn control register The DMACCnControl is a RW register which contains control information about the DMA channel n, such as transfer size, burst size and transfer width. The DMACCnControl bit assignments are given in Table 299. Software programs the DMACCnControl register directly before the appropriate DMA channel is enabled.
Page 348 BS_DMA controller RM0082 Table 299. DMACCnControl register bit assignments (continued) Name Reset value Description Destination transfer width. This 3 bits field states the width of destination (resp. source) transfer, according to encoding: 3‘b000 = Byte (8 bit) 3‘b001 = Halfword (16 bit) 3‘b010 = Word (32 bit) [23:21] Dwidth...
Page 349: Table 300. Dmac Configuration Register Bit Assignments
RM0082 BS_DMA controller Table 299. DMACCnControl register bit assignments (continued) Name Reset value Description Source burst size. This 3 bits field indicates the number of transfers that make up a destination (resp. source) burst transfer request, according to the encoding: 3‘b000 = 1 3‘b001 = 4 3‘b010 = 8...
Page 350 BS_DMA controller RM0082 Table 300. DMAC Configuration register bit assignments (continued) Name Reset value Description Lock. Setting this bit, locked transfers are enabled: when a burst occurs, the HLOCK signal is asserted by the DMAC, so that [16] 1’h0 the AHB arbiter doesn’t degrant the DMAC during the burst until the lock is deasserted, even if another master with greater priority requests the bus.
Page 351: Dmacperiphid Register
RM0082 BS_DMA controller Table 300. DMAC Configuration register bit assignments (continued) Name Reset value Description Source peripheral. This 4 bits field allows to select the DMA destination (resp. source) request peripheral. The value is ignored in case the SrcPeriphe [04:01] 4’h0 destination (resp.
Page 352: Table 301. Rtc Functional Registers Summary
BS_Real time clock RM0082 BS_Real time clock 20.1 Overview Within its basic subsystem, SPEAr300 provides a real time clock (RTC) acting as an APB slave. Main features of the RTC block are: ● Provides time-of-day clock in 24 hours mode.
Page 353: Table 302. Control Register Bit Assignments
RM0082 BS_Real time clock Table 302. CONTROL register bit assignments Reset Name Description value Interrupt event enable. Setting this bit, interrupt event is enabled, and interrupts [31] generated by alarm logic are sent out (see ALARM TIME and ALARM DATE registers). [30:10] Reserved Read: undefined.
Page 354: Table 304. Time Register Bit Assignments
BS_Real time clock RM0082 Table 303. STATUS register bit assignments (continued) Reset Name Type Description value Write to TIME register lost. If a second write to TIME register is requested before the [04] first is completed, this second request is aborted and the LT bit is set.
Page 355: Table 305. Date Register Bit Assignments
RM0082 BS_Real time clock 20.2.6 DATE register The DATE is a RW register which defines the date (year, month, day) when the RTC can start to count the time. The DATE register bit assignments are given in Table 305. Note: All values in this DATE register are in binary-coded decimal (BCD) format.
Page 356: Table 307. Alarm Date Register Bit Assignments
BS_Real time clock RM0082 20.2.8 ALARM DATE registers The ALARM DATE is a RW register which defines a successive date, so that when the value of DATE register is equal to the value set in this ALARM DATE register, an interrupt is generated (if enabled, that is if IE bit in CONTROL register is set).
Page 357: Overview
21.1 Overview Within its Application Connection Subsystem, SPEAr300 provides one Channel Control Co- processor (C3). C3 is a high-performance instruction driven DMA based co-processor. It executes instruction flows generated by the host processor. After it has been set-up by the host it runs in a completely autonomous way (DMA data in, data processing, DMA data out), until the completion of all the requested operations.
Page 358: Table 310. C3 Device Summary
AS_Cryptographic co-processor (C3) RM0082 Channel 3 - Unified Hash with HMAC Channel ID: 0x0000_4002 Supported Algorithms – – Hash with 128 bit digest – HMAC – SHA1 – Hash with 160 bit digest – HMAC – FIFO Size – Input FIFO: 16x32 bits –...
Page 359: Figure 35. C3 Block Diagram
RM0082 AS_Cryptographic co-processor (C3) 21.3 Block diagram Figure 35. C3 block diagram Reset Buffer (RAM) IDS (Inst.Disp.Subsys) Channel #0 Channel #1 AMBA AHB 2.0 Channel #2 Channel #7 SIF(AHB Slave Interface) 21.4 Main functions description C3 is a highly programmable DMA based hardware co-processor that executes some instructions flows (programs) written in memory by the host processor.
Page 360: Hif (High Speed Bus Interface)
AS_Cryptographic co-processor (C3) RM0082 Such applications can be found in the fields of security (data encryption, integrity check, etc.) and networking. There are many other fields of application for C3, such as signal processing, image processing and in general applications that require complex mathematical computations 21.4.1 HIF (High speed bus interface) This block implements an AMBA AHB 2.0 compliant Master interface.
Page 361: Ccm (Coupling/Chaining Module)
RM0082 AS_Cryptographic co-processor (C3) The channel main features are the following: ● Decoding of the instructions received from the dispatcher sub-system. ● DMA engine with support of scatter and gather operations. ● Internal input / output data-flows buffering by the means of FIFO in order to accommodate for the system bus latency.
Page 362: Table 311. C3 Components System Register Summary
AS_Cryptographic co-processor (C3) RM0082 21.5 Processing overview This section outlines the main steps involved in setting up C3 for processing. ● The host processor creates a program and stores it in memory. ● The program contains C3 instructions and their arguments (usually pointers to data buffers in system memory).
Page 363: System Registers (C3_Sys)
RM0082 AS_Cryptographic co-processor (C3) Table 311. C3 components system register summary (continued) Symbol Name Offset Reset Value unused 0x0800 32’h400 unused 0x0C00 32’h400 C3_ID0 Instruction Dispatcher #0 Registers 0x1000 32’h400 C3_ID1 unused 0x1400 32’h400 C3_ID2 unused 0x1800 32’h400 C3_ID3 unused 0x1C00 32’h400 C3_CH0...
Page 364: Table 312. C3 Components System Registers Map
AS_Cryptographic co-processor (C3) RM0082 21.6.3 Register configuration Table 312 summarizes AHB mapped registers for the system (SYS). Table 312. C3 components system registers map Symbol Name Type Reset value Offset SYS_SCR Status and control register 0x000 SYS_STR Channel status register 0x040 SYS_VER Hardware version and revision...
Page 365 RM0082 AS_Cryptographic co-processor (C3) the ones in the Instruction Dispatcher Status and Control Register (ID_SCR) of each ID. These bits allow knowing the status of all Instruction Dispatcher with a single AHB slave read. See the Instruction Dispatcher document section for more details Bit 23 to 20 - Instruction dispatcher n interrupt status (ISDn) Interrupt States (IS) of every Instruction Dispatcher are made available in these bits.
Page 366 AS_Cryptographic co-processor (C3) RM0082 Bit 16 - Asynchronous master reset (ARST) The whole C3 can be reset using this bit. The reset is done asynchronously in Hardware thus guaranteeing a well known state after its execution. A special Hardware block takes care of correct timings for the reset sequence.
Page 367 RM0082 AS_Cryptographic co-processor (C3) Bit 31 to 0 - Channel n status (CnS) The status of each Channel is mirrored in these bits. The lower 16 bits (bits 15 to 0) are the same ones as found in the Instruction Dispatcher Status and Control Register (ID_SCR) and in the System Status and Control Register (SYS_SCR).
Page 368: Master Interface Register (C3_Hif)
AS_Cryptographic co-processor (C3) RM0082 Initial Value Type Bit 31 to 24 - Hardware Version Bits V7-V0 represents the Version. This is always 3 (the v3 part in C3v3). Bit 23 to 16 - Hardware Revision Bits R7-R0 represents the RTL Revision. Bit 15 to 0 - Hardware Sub-revision Bits S15-S0 represents the RTL Sub-revision.
Page 369: Table 313. Ahb Mapped Registers For Master Interface (Hif)
RM0082 AS_Cryptographic co-processor (C3) Read transactions from this address window are not affected by the Byte Bucket: they are normally routed either to the Internal Memory or to the Bus. Transaction requests coming from IDs or Channels that are within an address window of 64 KB starting from the programmed Memory Base Address (HIF_MBAR) will be routed to the Internal Memory.
Page 370: Register Description
AS_Cryptographic co-processor (C3) RM0082 Zero is read from undefined locations, writing has no effect. 21.6.7 Register Description 21.6.8 Memory page (HIF_MP) A 512 Bytes page of the Internal Memory is mapped in the Memory Page address range (HIF_MP, 0x000 to 0x1FF). The page number to be mapped is programmed using the Memory Page Base Address Register (HIF_MPBAR).
Page 371: Memory Base Address Register (Hif_Mbar)
RM0082 AS_Cryptographic co-processor (C3) 21.6.10 Memory base address register (HIF_MBAR) The Base Address of the Internal Memory can be programmed to any multiple of 64 KB. Bits 31-16 of MBAR are used for this. Channel and Instruction Dispatcher transactions that fall within a window of 64 KB starting from MBAR are then routed to the Internal Memory (if enabled).
Page 372 AS_Cryptographic co-processor (C3) RM0082 Symbol Initial Value Type Symbol DAIR DAIW Initial Value Type Symbol Initial Value Type Symbol Initial Value Type ● Bit 31 to 18, 15 to 1 - Reserved These bits are reserved and should be set to zero. Bit 17 - Disable Auto Increment on Read (DAIR) Bit 17 Description...
Page 373: Memory Page Base Address Register (Hif_Mpbar)
RM0082 AS_Cryptographic co-processor (C3) Bit 16 - Disable Auto Increment on Write (DAIW) Bit 16 Description DAIR Memory Access Address Register (HIF_MAAR) is auto 1’b0 incremented when an Internal Memory location is read from AHB using the Memory Access Data Register (HIF_MADR). Memory Access Address Register (HIF_MAAR) auto increment 1’b1 is disabled on HIF_MADR writes.
Page 374: Memory Access Address Register (Hif_Maar)
AS_Cryptographic co-processor (C3) RM0082 Initial Value Type A 512 Bytes page of the Internal Memory is mapped on the AHB address space HIF_MP (0x000 to 0x01FF). The page is selected using bits P15-P9 of this registers. Bits B31-B16 (read-only) are those programmed in the Internal Memory Base Address Register (HIF_MBAR).
Page 375: Memory Access Data Register (Hif_Madr)
RM0082 AS_Cryptographic co-processor (C3) 21.6.14 Memory access data register (HIF_MADR) The Internal Memory location which address is programmed in the Memory Access Address Register (HIF_MAAR) can be accessed reading and writing the Memory Access Data Register (HIF_MADR). By default, when reading or writing the Memory Access Data Register, the Memory Access Address Register is auto incremented.
Page 376: Byte Bucket Control Register (Hif_Ncr)
AS_Cryptographic co-processor (C3) RM0082 21.6.16 Byte bucket control register (HIF_NCR) The Byte Bucket must be enabled to allow Channels and Instruction Dispatchers to discard data using it. This is done using the Enable Byte Bucket Mapping bit (ENM). The correct procedure for the Software to enable the Byte Bucket is to first program its base address using HIF_NBAR and then enable it by setting the ENM bit of HIF_NCR.
Page 377: Table 314. Ahb Mapped Registers For An Instruction Dispatcher (Id)
RM0082 AS_Cryptographic co-processor (C3) 21.6.17 Instruction dispatcher registers (C3_IDn) Up to four Instruction Dispatchers can exist in Hardware. Each Instruction Dispatcher has its own set of registers. Register Configuration Table 314. summarizes AHB mapped registers for an Instruction Dispatcher (ID). Table 314.
Page 378 AS_Cryptographic co-processor (C3) RM0082 Bit 31 to 30 - Instruction Dispatcher Status (IDS) The Instruction Dispatcher Status bits (IDSn) indicates the state in which the addressed Instruction Dispatcher (ID) is. The Software can use these bits at system startup to know if an ID is present.
Page 379 RM0082 AS_Cryptographic co-processor (C3) Bit 26 DERR Description The Channel to which the current instruction was addressed is 1’b1 in error state or went to error state executing the instruction. (Cleaning Conditions) This flag is cleared in three ways: 1’b0 resetting the Instruction Dispatcher, launching a new program or requesting an asynchronous master reset.
Page 380 AS_Cryptographic co-processor (C3) RM0082 Bit 22 - Interrupt Enable on Stop (IES) Bit 22 IES Description The Instruction Dispatcher generates an Interrupt on normal 1’b1 termination of a program execution (when the stop instruction executes). Do not generate Interrupt. Cleaning this bit does not clear 1’b0 pending interrupts.
Page 381 RM0082 AS_Cryptographic co-processor (C3) Bit 17 - Ignore Errors (IGR) Not implemented. This bit should be set to zero. Bit 16 - Reset Command (RST) Each Instruction Dispatcher can be reset independently from each other using this bit. In Hardware the reset is done synchronously and not all registers are affected by it. The following are the effects of a synchronous reset: ●...
Page 382: Table 315. Ahb Mapped Registers For Channel (Ch)
AS_Cryptographic co-processor (C3) RM0082 Instruction Word 0-3 Register (ID_IRn) Instruction Word Registers are used to read back the OP Code of the current executing instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is undefined for 3 word instructions.
Page 383: Table 316. Channel Id Table
RM0082 AS_Cryptographic co-processor (C3) in charge of maintaining the corresponding version of the channel. In the device, the bit mask to be used for retrieving this ID is 0x8000_0000. Table 316. Channel ID Table Channel Channel Name Function Type Channel ID EMPTY_CNL No channel DES/3DES algorithm (ECB,...
Page 384: Table 317. Des Ecb Start Instruction Bit Encoding
AS_Cryptographic co-processor (C3) RM0082 21.8.5 The DES START ECB instruction is 2 words long. This instruction is used to set the key for the following operations. The length of the key is encoded in the first instruction word, while the second word represents the Source Address for the key. Table 317.
Page 385: Table 321. Des Ecb Append Instruction Bit Encoding
RM0082 AS_Cryptographic co-processor (C3) Bits ‘a’ and ‘b’ in the above table are used to set the algorithm and the operation to perform and have the same encoding as in the ECB instruction. Bits 15 to 0 in the first instruction word (cccc in the above table) represent the length in Bytes of the key.
Page 386: Table 322. Des Cbc Append Instruction Bit Encoding
AS_Cryptographic co-processor (C3) RM0082 instruction word, the second word represents the Source Address and the third word represents the Destination Address. Table 322. DES CBC Append Instruction Bit Encoding Bit Encoding xxxx 10ab 101x xxxx cccc cccc cccc cccc 32 bit Source Address for the data 32 bit Destination Address for the data Bits ‘a’...
Page 387: Feedback Registers (Des_Feedback)
RM0082 AS_Cryptographic co-processor (C3) 21.8.13 Feedback registers (DES_FEEDBACK) The Feedback Registers contain the value that is added to the DES input for implementing the selected mode of operation (it depends on the selected mode). 21.8.14 Control and status register (DES_CONTROL_STATUS) Symbol Initial Value Type...
Page 388: Tkey Registers (Des_Key)
AS_Cryptographic co-processor (C3) RM0082 Bit 1 Description 1’b0 1’b1 Bit 0 - Algorithm (ALGO) This bit indicates the algorithm to use (DES or 3DES). Bit 1 Description 1’b0 1’b1 3DES 21.8.15 TKey registers (DES_KEY) The Key Registers contain the key. 21.8.16 Channel ID (DES_ID) The Channel ID register contains the Identifier of this version of the DES channel.
Page 389: Table 324. Aes Ecb Start Instruction Bit Encoding
RM0082 AS_Cryptographic co-processor (C3) 21.9.4 AES START instruction The AES START instruction can be applied with 3 different modes of operation: ● ● ● 21.9.5 The AES START ECB instruction is 2 words long. This instruction is used to set the key for the following operations.
Page 390: Table 327. Aes Ctr Start Instruction Bit Encoding
AS_Cryptographic co-processor (C3) RM0082 21.9.7 The AES START CTR instruction is 3 words long. This instruction is used to set the key and the initialization vector for the following operations. The length of the key is encoded in the first instruction word, while the second word represents the Source Address for the key. Table 327.
Page 391: Table 329. Aes Cbc Append Instruction Bit Encoding
RM0082 AS_Cryptographic co-processor (C3) 21.9.10 The AES APPEND CBC instruction is 3 words long. This instruction is used for passing the data to process (encrypt or decrypt). The length of the data to process is encoded in the first instruction word, the second word represents the Source Address and the third word represents the Destination Address.
Page 392: Data Input/Output Registers (Aes_Datain_Out)
AS_Cryptographic co-processor (C3) RM0082 Table 331. AES registers map (continued) Symbol Name Type Initial value Address AES_DATA_INOUT2 Data Input/output register #2 R/W 32’h0 0x008 AES_DATA_INOUT3 Data Input/output register #3 R/W 32’h0 0x00C AES_FEEDBACK0 Feedback register #0 32’h0 0x010 AES_FEEDBACK1 Feedback register #1 32’h0 0x014 AES_FEEDBACK2...
Page 393: Counter Registers (Aes_Counter)
RM0082 AS_Cryptographic co-processor (C3) 21.10.4 Counter registers (AES_COUNTER) The Counter Registers contain the counter used in CTR mode (that will be automatically incremented). 21.10.5 Control and status register (AES_CONTROL_STATUS) Symbol KEYSZ1 KEYSZ0 MODE2 MODE1 MODE0 KEYRDY CTXSR1 Initial Value Type Symbol CTXSR0 res Initial Value...
Page 394 AS_Cryptographic co-processor (C3) RM0082 Bit 30 to 29 Description 2’b00 128 bits 2’b01 192 bits 2’b10 256 bits 2’b11 Not Used Bits 28 to 26 - Mode of operation (MODE) These 3 bits represent the mode of operation, as in the following internal representation. For writing this field the bit #2 of the input word has to be set to 1.
Page 395: Key Registers (Aes_Key)
RM0082 AS_Cryptographic co-processor (C3) Bits 22 to 0 - Reserved These bits are reserved and should be written zero. 21.10.6 Key registers (AES_KEY) The Key Registers contain the key. 21.10.7 Channel ID (AES_ID) The Channel ID register contains the Identifier of this version of the AES channel. The Channel ID for this version of the AES channel is 0x0000_3000.
Page 396: Table 332. Hash Init Instruction Bit Encoding
AS_Cryptographic co-processor (C3) RM0082 21.11.5 INIT The HASH [MD5/SHA1/SHA2] INIT instruction is 1 word long. This instruction is used to set the Function. Table 332. HASH INIT Instruction bit encoding Bit Encoding xxxx 000a a00x xxxx cccc cccc cccc cccc Bits ‘aa’...
Page 397: Table 335. Hash End Instruction Bit Encoding
RM0082 AS_Cryptographic co-processor (C3) Table 335. HASH END Instruction bit encoding Bit Encoding xxxx 010a a01t xxxx cccc cccc cccc cccc 32 bit Destination Address for the message Bits ‘aa’ in the above table are used to set the algorithm to use and have the same encoding as in the INIT instruction(Table 333.).
Page 398: Table 338. Hmac Init Instruction Bit Encoding
AS_Cryptographic co-processor (C3) RM0082 21.11.11 HMAC instruction There are 4 different HMAC instructions: ● HMAC MD5 ● HMAC SHA1 ● HMAC CONTEXT The first 3 instructions are used for computing the HMAC of a message and work in the same way. The last one is used for saving and restoring the context. 21.11.12 HMAC [MD5/SHA1] instructions Each HMAC [MD5/SHA1] instruction is composed by 3 sub-instructions: ●...
Page 399: Table 340. Hmac End Instruction Bit Encoding
RM0082 AS_Cryptographic co-processor (C3) Bits 15 to 0 in the first instruction word (cccc in Table 339) represent the Count in Bytes of the input message. Note: The state of the HASH channel should be saved after an HMAC-APPEND instruction, if a consecutive HMAC-APPEND instruction is to be executed.
Page 400: Table 341. Hmac Context Save Instruction Bit Encoding
AS_Cryptographic co-processor (C3) RM0082 Table 341. HMAC CONTEXT SAVE Instruction bit encoding Bit Encoding xxxx 0111 10xx xxxx cccc cccc cccc cccc 32 bit Destination Address for the context 21.11.18 RESTORE The HMAC CONTEXT RESTORE instruction is 2 words long. This instruction is used to set the Source Address Register for the context and to restore the full context.
Page 401 RM0082 AS_Cryptographic co-processor (C3) Table 343. UHH channel registers map (continued) Symbol Name Type Initial value Address UHH_WX0 Message Scheduler #0 32’h0 0x064 UHH_WX1 Message Scheduler #1 32’h0 0x068 UHH_WX2 Message Scheduler #2 32’h0 0x06C UHH_WX3 Message Scheduler #3 32’h0 0x070 UHH_WX4 Message Scheduler #4...
Page 402: Register Description
AS_Cryptographic co-processor (C3) RM0082 Table 343. UHH channel registers map (continued) Symbol Name Type Initial value Address UHH_DATA_IN CB Status &Control Register 32’h0 0x0EC UHH_CB_CONTROL_ CB Status &Control Register R/(W) 32’h0 0x200 STATUS UHH_CU_CONTROL_ 32'h8000_000 CU Status and Control Register R/(W) 0x200 STATUS...
Page 403 RM0082 AS_Cryptographic co-processor (C3) Bit 31 to 30 - Channel Status (CS) These two bits represent the status of the Channel. The status is reported to the Instruction Dispatcher (which also duplicates this information in its bits SCR_CnS). Bit 31 CSH Bit 30 CSL Description Not Present: This Channel does not exist in Hardware.
Page 404 AS_Cryptographic co-processor (C3) RM0082 Bit 27 BERR Description The Channel was requested to become a Chaining-master, or 1’b1 simultaneously both a Couple-Master and a Slave for cascade CCM operations. (Clearing conditions) This flag is cleared in two ways: resetting 1’b0 the UHH Channel or requesting an asynchronous master reset.
Page 405: Data Input Register (Uhh_Data_In)
RM0082 AS_Cryptographic co-processor (C3) Bit 15 to 0 - Reserved These bits are reserved and should be written zero. 21.11.22 Data input register (UHH_DATA_IN) The Data Input Register contains the current data input word to the UHH Channel. 21.11.23 Control and status register (UHH_CB_CONTROL_STATUS) The UHH_CB_CONTROL_STATUS bit assignments are given.
Page 406 AS_Cryptographic co-processor (C3) RM0082 Bit 25 to 22 Status Description 4’b0000 BLOCK_IDLE Idle State 4’b0001 HASH_DO_RESET Init for hash 4’b0010 HASH_REQUEST_DATA Get data input for hash 4’b0011 HASH_PROCESS_DATA Process the message 4’b0100 HMAC_DO_RESET_SHORT_KEY Init for HMAC with short key 4’b0101 HMAC_DO_RESET_LONG_KEY Init for HMAC with long key 4’b0110...
Page 407 RM0082 AS_Cryptographic co-processor (C3) Bit 17 to 16 Algorithm 2’b00 2’b01 SHA-1 2’b10 Not Used 2’b11 Not Used Bits 15 to 0 - Reserved These bits are reserved and should be written zero. Core Status Register (UHH_SR) Symbol ALG1 ALG0 CPHA1 CPHA0 PST2...
Page 408 AS_Cryptographic co-processor (C3) RM0082 Bit 31 to 30 Algorithm 2’b00 2’b01 SHA-1 2’b10 Not Used 2’b11 Not Used Bits 29 to 27 - Reserved These bits are reserved and should be written zero. Bits 26 to 25 - Current Phase (CPHA) These bits represent the current phase of the hash algorithm.
Page 409 RM0082 AS_Cryptographic co-processor (C3) Bit 17 to 14 ST Description 4’b0110 Pad short outer key 4’b0111 Wait for the HMAC 4’b1000 HMAC value is ready 4’b1001 Get long inner key 4’b1010 Get long outer key 4’b1011 Wait for long inner key preparation 4’b1100 Wait for long outer key preparation 4’b1101...
Page 410: Channel Id (Uhh_Ch_Id)
AS_Cryptographic co-processor (C3) RM0082 Bit 0 - Reserved This bit is reserved and should be written zero. Hash Status Registers (UHH_HX0 - UHH_HX7) The Hash Status Registers contain the current partial value of the digest. Hash Working Registers (UHH_X0 - UHH_X7) The Hash Working Registers contain a temporary value used for the computation of the digest.
Page 411: Overview
RM0082 HS_USB2.0 host HS_USB2.0 host 22.1 Overview Within its High-Speed (HS) Connection Subsystem, the device provides one USB 2.0 Host with 2 physical ports which are fully compliant with the Universal Serial Bus specification (version 2.0), and offering an interface to the industry-standard AHB bus. Main features provided by USB 2.0 Host are listed below: ●...
Page 412: Figure 36. Uhc Block Diagram
HS_USB2.0 host RM0082 22.2 Block diagram Figure 36. UHC block diagram. EHCI Port0 Generator Operation EHCI List Processor Port1 Packet Buffer USB2.0 EHCI Controller OHCI USB1.1 OHCI Controller OHCI USB1.1 OHCI Controller 22.3 Main functions description 22.3.1 AHB bus interface unit (BIU) USB 2.0 Host access to the AHB bus is granted by the AHB Bus Interface Unit (BIU), which consists of a Master module and a Slave module.
Page 413: Ohci Host Controller
RM0082 HS_USB2.0 host Major blocks of the EHCI Host Controller are described in Section 22.4: EHCI host controller blocks 22.3.3 OHCI host controller Two OHCI Host Controllers compliant with the OHCI specification (version 1.0a) are also integrated in the UHC to support the 12 Mbps full-speed (FS) and the 1.5 Mbps low-speed (LS) operation of USB 1.1.
Page 414: Root Hub
HS_USB2.0 host RM0082 According to its functionality, the PBUF block interface with both the List Processor and the Root Hub. Specifically, during an OUT transaction, the List Processor fetches data from the system memory and writes them in the PBUF. Besides, during an IN transaction, the data are written to PBUF by the Root Hub Section 22.4.5: Root hub.
Page 415: Figure 37. Usb Host Controller (Uhostc) Block Diagram
RM0082 HS_USB2.0 host Figure 37. USB Host controller (UHOSTC) block diagram OHCI Regs RCFG_RegData(32) Port TxEnL Slave Ctrl APB_SADR(6) block Ctrl TxDpls State Root Hub Control APB_SData(32) TxDmns Port & HCI_Data(32) Host SIE Ctrl OHCI Cntl Control Regs List Ctrl Processor Block Clock...
Page 416: List Processor Block
HS_USB2.0 host RM0082 22.5.3 List processor block The list processor block acts as a main controller of the entire controller. It has multiple state machines to implement List Service Flow, List Priority, USB-States, ED, TD Service, StatusWriteBack, TD Retirement, and so on as per the OHCI specification. Additionally, this block implements a controller which interfaces with HCI_master and hsie, helping them in the data transfer from system memory to USB and USB to system memory.
Page 417: Table 344. External Pin Connections
RM0082 HS_USB2.0 host 22.5.7 RootHub port configuration The port configuration block implements part of the RootHub logic. This block is separated from the main RootHub block to distinguish the logic that varies with design requirements. In short, this block implements part of the OHCI registers that are specific to RootHub and a state machine for every DownStreamPort to control the port functional states.
Page 418: Table 345. Uhc Registers' Base Address
HS_USB2.0 host RM0082 Similarly, OHCI block generates one interrupt when any of the following conditions occurs: ● OwnershipChange ● RootHubStatusChange ● FrameNumberOverflow ● UnrecoverableError ● ResumeDetected ● StartofFrame ● WritebackDoneHead ● SchedulingOverrun But this interrupt is generated only when corresponding bits are enabled in Table 370: HcInterruptEnable register bit assignments,...
Page 419: Table 346. Ehci Host Controller Capability Registers Summary
RM0082 HS_USB2.0 host Note: Each auxiliary power well register is only reset (that is, initialized to its default value) by hardware in case of initial power-up of the auxiliary power well, or in response to a host controller reset (HCRESET bit set to 1‘b1 in USBCMD register). ●...
Page 420: Table 349. Ehci Host Controller Specific Registers Summary
HS_USB2.0 host RM0082 Table 349. EHCI host controller specific registers summary Size Name Offset Type Reset value Description (bit) Programmable microframe INSNREG00 USBOPBASE+0x80 14’h0 base value. Programmable packet buffer INSNREG01 USBOPBASE+ 0x84 32’h00200020 out/in thresholds. Programmable packet buffer INSNREG02 USBOPBASE+0x88 12’h080 depth.
Page 421: Table 351. Hccapbase Register Bit Assignments
RM0082 HS_USB2.0 host Table 350. Host controller operational registers (continued) Offset Register name HcRhStatus HcRhPortStatus[1] 54+4*NDP HcRhPortStatus[NDP] 22.6.4 Register descriptions of EHCI 22.6.5 HCCAPBASE register The HCCAPBASE is a RO register which contains the base address of the DWord-aligned memory-mapped EHCI host controller capability registers. The HCCAPBASE register bit assignments are given in Table 351.
Page 422 HS_USB2.0 host RM0082 Table 352. HCSPARAMS register bit assignments (continued) Name Reset value Description [19:17] Reserved Read: undefined. Port indicators. This bit indicates whether the ports support port indicator control. When this bit is set, each port status [16] P_INDICATOR 1‘h0 control register (PORTSC) of auxiliary power well includes a specific RW field (PIC, port indicator...
Page 423: Table 353. Hccparams Register Bit Assignments
RM0082 HS_USB2.0 host Table 352. HCSPARAMS register bit assignments (continued) Name Reset value Description Port power control. This field indicates whether the EHCI host controller implementation includes port power control. In particular, setting this bit a port power switch is [04] 1’h1 enabled for each port, otherwise (PPC set to 1‘b0)
Page 424: Usbcmd Register
HS_USB2.0 host RM0082 Table 353. HCCPARAMS register bit assignments (continued) Name Reset value Description Isochronous scheduling threshold. This field indicates, relative to the current position of the executing EHCI host controller, where software can reliably update the isochronous schedule. When bit [7] of this field is 1‘b0 (default), the value of the least significant 3 bits indicates the number of micro- [07:04]...
Page 425: Table 354. Usbcmd Register Bit Assignments
RM0082 HS_USB2.0 host Note: Writing this register causes a command to be executed. The USBCMD register bit assignments are given in Table 354. Table 354. USBCMD register bit assignments Name Reset value Description [31:24] Reserved Read: undefined. Write: should be zero. Interrupt threshold control.
Page 426 HS_USB2.0 host RM0082 Table 354. USBCMD register bit assignments (continued) Name Reset value Description Light host controller reset. This bit allows the driver to reset the EHCI host controller without affecting the state of the ports or the relationship to the companion OHCI host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit (in CONFIGFLAG register setting should not go to zero...
Page 427 RM0082 HS_USB2.0 host Table 354. USBCMD register bit assignments (continued) Name Reset value Description Frame list size. This 2 bit field specifies the size of the frame list, according to encoding: 2‘b00 = 102 elements (4096 bytes). 2‘b01 = 512 elements (2048 bytes). [03:02] 2‘h0 2‘b10 = 256 elements (1024 bytes) - for resource-...
Page 428: Table 355. Usbsts Register Bit Assignments
HS_USB2.0 host RM0082 22.6.9 USBSTS register The USBSTS is a RW register which indicates pending interrupts and various states of the EHCI host controller. The USBSTS register bit assignments are given in Table 355. Note: The status resulting from a transaction on the serial bus is not indicated in this register. Software clears a bit in this register by writing a 1‘b1 to it.
Page 429 RM0082 HS_USB2.0 host Table 355. USBSTS register bit assignments (continued) Name Reset value Description Interrupt on async advance. This status bit indicates the assertion of that interrupt source. System software can force the EHCI host [05] 1‘h0 controller to issue an interrupt the next time the EHCI host controller advances the asynchronous schedule by setting the interrupt on async advance doorbell bit (IAAD) in the USBCMD register.
Page 430: Table 356. Usbintr Register Bit Assignments
HS_USB2.0 host RM0082 Table 355. USBSTS register bit assignments (continued) Name Reset value Description USB error interrupt. This bit is set by the EHCI host controller when completion of a USB transaction results in an error [01] USBERRINT 1‘h0 condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
Page 431: Table 357. Frindex Register Bit Assignments
RM0082 HS_USB2.0 host Table 356. USBINTR register bit assignments (continued) Name Reset value Description When both this bit and the port change detect (PGD) bit in the USBSTS register are set, the EHCI host Port Change controller will issue an interrupt. [02] 1‘h0 Interrupt Enable...
Page 432: Table 358. Usbcmd Register Encoding
HS_USB2.0 host RM0082 Table 358. USBCMD register encoding FLS field value Number of elements 2‘b00 1024 2‘b01 2‘b10 2‘b11 Reserved The SOF frame number value for the bus SOF token is derived or alternatively managed from this register. The value of FRINDEX must be 125 µsec (1 micro-frame) ahead of the SOF token value.
Page 433: Table 359. Periodiclistbase Register Bit Assignments
RM0082 HS_USB2.0 host The contents of this register are combined with the FRINDEX register to enable the EHCI host controller to step through the periodic frame list in sequence. Note: System software loads this register prior to starting the schedule execution by the EHCI host controller.
Page 434: Table 361. Configflag Register Bit Assignments
Each EHCI host controller must implement one or more port status and control (PORTSC) registers. The actual number of PORTSC registers implemented by the EHCI host controller is reported in the N_PORTS field of the HCSPARAMS register. For SPEAr300 implementation this value is 4’h2 then two ports are available.
Page 435 RM0082 HS_USB2.0 host Table 362. PORTSC register bit assignments (continued) Reset Name Description value Port indicator control. Writing to these 2 bit field has no effect if the P_INDICATOR bit in the HCSPARAMS register is cleared. If P_INDICATOR bit is set to 1‘b1, then the PIC encoding is: 2‘b00 = Port indicators are off.
Page 436 HS_USB2.0 host RM0082 Table 362. PORTSC register bit assignments (continued) Reset Name Description value Line status. This 2 bit field reflects the current logical levels of the D+ (bit [11]) and D- (bit [10]) signal lines, according to encoding: 2‘b00 SE0 = Not low-speed device, perform EHCI reset. 2‘b01 J-state = Not low-speed device, perform EHCI reset.
Page 437 RM0082 HS_USB2.0 host Table 362. PORTSC register bit assignments (continued) Reset Name Description value Suspend. This bit states whether the port is in suspend, according to encoding: 1‘b0 = Port is not in suspend state. 1‘b1 = Port is in suspend state. This S bit together with the port enabled bit (PEN) in this register define the port states as follows: 1‘b0 1‘bx = Disabled.
Page 438 HS_USB2.0 host RM0082 Table 362. PORTSC register bit assignments (continued) Reset Name Description value Force port resume. This bit states whether the port is in suspend, according to encoding: 1‘b0 = No resume (K-state) detected/driven on port. 1‘b1 = Resume detected/driven on port. The functionality defined for manipulating this bit depends on the value of the suspend bit (see above).
Page 439: Insnreg00 Register
RM0082 HS_USB2.0 host Table 362. PORTSC register bit assignments (continued) Reset Name Description value Port enabled/disabled. This bit states whether the port is enabled, according to encoding: 1‘b0 = Disabled. 1‘b1 = Enabled. Ports can only be enabled by the EHCI host controller as a part of the reset and enable.
Page 440: Table 363. Insnreg01 Register Bit Assignments
HS_USB2.0 host RM0082 memory feature is driven by the INSNREG03 register. The INSNREG01 register bit assignments are given in Table 363. Table 363. INSNREG01 register bit assignments Name Reset value Description [31:16] 16’h0020 Out transactions threshold (in bytes). [15:00] 16’h0020 In transactions threshold (in bytes).
Page 441: Table 366. Hcrevision Register Bit Assignments
RM0082 HS_USB2.0 host divided into four partitions, specifically for Control and Status, Memory Pointer, Frame Counter and Root Hub. All of the registers should be read and written as Dwords. Reserved bits may be allocated in future releases of this specification. To ensure interoperability, the Host Controller Driver that does not use a reserved field should not assume that the reserved field contains 0.
Page 442 HS_USB2.0 host RM0082 Table 367. HcControl register bit assignments (continued) Read/Write Bits Name Reset Description HCD HC RemoteWakeupConnected This bit indicates whether HC supports remote wakeup signaling. If remote wakeup is supported and used by the system it is the responsibility of system firmware to set [09] this bit during POST.
Page 443: Hccommandstatus Register
RM0082 HS_USB2.0 host Table 367. HcControl register bit assignments (continued) Read/Write Bits Name Reset Description HCD HC ControlListEnable This bit is set to enable the processing of the Control list in the next Frame. If cleared by HCD, processing of the Control list does not occur after the next SOF.
Page 444: Table 368. Hccommandstatus Register Bit Assignments
HS_USB2.0 host RM0082 to the Host Controller without concern for corrupting previously issued commands. The Host Controller Driver has normal read access to all bits. The SchedulingOverrunCount field indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This occurs when the Periodic list does not complete before EOF.
Page 445: Hcinterruptstatus Register
RM0082 HS_USB2.0 host Table 368. HcCommandStatus register bit assignments (continued) Read/Write Bits Name Reset Description ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. It is set by HCD whenever it adds a TD to an ED in the Control list.
Page 446: Table 369. Hcinterruptstatus Register Bit Assignments
HS_USB2.0 host RM0082 Table 369. HcInterruptStatus register bit assignments Read/Write Bits Name Reset Description [31] Reserved OwnershipChange This when sets OwnershipChangeRequest field in HcCommandStatus. [30] This event, when unmasked, will always generate an System Management Interrupt (SMI) immediately. This bit is tied to 0b when the SMI pin is not implemented. [29:07] Reserved RootHubStatusChange...
Page 447: Table 370. Hcinterruptenable Register Bit Assignments
RM0082 HS_USB2.0 host 22.6.29 HcInterruptEnable register Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the corresponding bit in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus.
Page 448: Table 371. Hcinterruptdisable Register Bit Assignments
HS_USB2.0 host RM0082 HcInterruptEnable register. Thus, writing a '1' to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current value of the HcInterruptEnable register is returned.
Page 449: Table 372. Hchcca Register Bit Assignments
RM0082 HS_USB2.0 host Table 372. HcHCCA register bit assignments Read/Write Bits Name Reset Description This is the base address of the Host Controller [31:08] HCCA Communication Area. [07:00] Reserved 22.6.33 HcPeriodCurrentED register The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor.
Page 450: Table 375. Hccontrolcurrented Register Bit Assignments
HS_USB2.0 host RM0082 Table 375. HcControlCurrentED register bit assignments Read/Write Bits Name Reset Description ControlCurrentED This pointer is advanced to the next ED after serving the present one. HC will continue processing the list from where it left off in the last Frame. When it reaches the end of the Control list, HC checks the ControlListFilled of in HcCommandStatus.
Page 451: Table 377. Hcbulkcurrented Register Bit Assignments
RM0082 HS_USB2.0 host Table 377. HcBulkCurrentED register bit assignments Read/Write Bits Name Reset Description BulkCurrentED This is advanced to the next ED after the HC has served the present one. HC continues processing the list from where it left off in the last Frame. When it reaches the end of the Bulk list, HC checks the ControlListFilled of HcControl.
Page 452: Table 379. Hcfminterval Register Bit Assignments
HS_USB2.0 host RM0082 Table 379. HcFmInterval register bit assignments Read/Write Bits Name Reset Description FrameIntervalToggle [31] R/W‘ HCD toggles this bit whenever it loads a new value to FrameInterval. FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame.
Page 453: Table 381. Hcfmnumber Register Bit Assignments
RM0082 HS_USB2.0 host 22.6.42 HcFmNumber register The HcFmNumber register is a 16 bit counter. It provides a timing reference among events happening in the Host Controller and the Host Controller Driver. The Host Controller Driver may use the 16 bit value specified in this register and generate a 32 bit frame number without requiring frequent access to the register.
Page 454: Table 383. Hclsthreshold Register Bit Assignments
HS_USB2.0 host RM0082 Table 383. HcLSThreshold register bit assignments Read/Write Bits Name Reset Description [31:12] Reserved LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed [11:00] 0628h transaction. transaction started only FrameRemaining ³...
Page 455: Table 384. Hcrhdescriptora Register Bit Assignments
RM0082 HS_USB2.0 host Table 384. HcRhDescriptorA register bit assignments Read/Write Bits Name Reset Description PowerOnToPowerGoodTime This byte specifies the duration HCD has to wait before POTP [31:24] accessing a powered-on port of the Root Hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms.
Page 456: Hcrhdescriptorb Register
HS_USB2.0 host RM0082 Table 384. HcRhDescriptorA register bit assignments (continued) Read/Write Bits Name Reset Description PowerSwitchingMode This bit is used to specify how the power switching of the Root Hub ports is controlled. It is implementation-specific. This field is only valid if the NoPowerSwitching field is cleared.
Page 457: Table 385. Hcrhdescriptorb Register Bit Assignments
RM0082 HS_USB2.0 host Table 385. HcRhDescriptorB register bit assignments Read/Write Bits Name Reset Description PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. When set, the port's power state is only affected by per- port power control (Set/ClearPortPower).
Page 458: Hcrhportstatus[1:Ndp] Register
HS_USB2.0 host RM0082 Table 386. HcRhStatus register bit assignments (continued) Read/Write Bits Name Reset Description (read) LocalPowerStatusChange The Root Hub does not support the local power status feature; thus, this bit is always read as ‘0’.(write) SetGlobalPower global power mode [16] LPSC (PowerSwitchingMode=0), This bit is written to ‘1’...
Page 459: Table 387. Hcrhportstatus Register Bit Assignments
RM0082 HS_USB2.0 host Table 387. HcRhPortStatus register bit assignments Read/write Bits Name Reset Description [31:21] Reserved PortResetStatusChange This bit is set at the end of the 10-ms port reset signal. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no [20] PRSC effect.
Page 460 HS_USB2.0 host RM0082 Table 387. HcRhPortStatus register bit assignments (continued) Read/write Bits Name Reset Description (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. When set, a Low Speed device is attached to this port. When clear, a Full Speed device is attached to this port.
Page 461 RM0082 HS_USB2.0 host Table 387. HcRhPortStatus register bit assignments (continued) Read/write Bits Name Reset Description (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit cannot be set if CurrentConnectStatus is cleared.
Page 462 HS_USB2.0 host RM0082 Table 387. HcRhPortStatus register bit assignments (continued) Read/write Bits Name Reset Description (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected.
Page 463: Table 388. Endpoints Assignment
In addition to single independent USB 2.0 hosts, within its high-speed (HS) connection subsystem SPEAr300 provides a USB 2.0 Device which is fully compliant with the universal serial bus specification (version 2.0), and offering an interface to the industry-standard AHB bus.
Page 464: Figure 38. Udc-Ahb Subsystem Block Diagram Within The Usb 2.0 Device
HS_USB 2.0 device RM0082 23.2 Block diagram Figure 38 shows the block diagram of the UDC-AHB subsystem. Figure 38. UDC-AHB subsystem block diagram within the USB 2.0 device External RAM (IN Endpoints) READ Port WRITE Port EP FIFO System EP FIFO EP FIFO CNTRL 1 Slave-only...
Page 465: Main Functions Description
RM0082 HS_USB 2.0 device 23.3 Main functions description 23.3.1 UTLI The USB transaction layer interface (UTLI) of the UDC-AHB subsystem interfaces with the UDC and the FIFOs to handle data reception/transmission with and USB host. Main tasks of UTLI are: ●...
Page 466: Sof Tracker
HS_USB 2.0 device RM0082 page 497), which are mapped into the address space of the global control and status registers (CSRs, Section 23.3.6: Control and status registers). Interrupt (IRQ24) issued will be the OR of all active events defined above, plus the plug detect interrupt.
Page 467: Figure 40. Rxfifo Implementation
RM0082 HS_USB 2.0 device accommodation is limited by the size of the OUT packets. Rest of the data FIFO i.e. 2 KB (out of total 4KB dada FIFO) is used for TXFIFO. Figure 40. RxFIFO implementation 32 bits wide 37 bits wide Data Address Addrss FIFO...
Page 468: Control And Status Registers
HS_USB 2.0 device RM0082 Each endpoint FIFO controller maintains the write and read pointers to access the memory where relevant TxFIFO is located. Besides, these controllers need both the base address and the buffer size of each endpoint TxFIFO to implement adaptive buffer management. This feature allows to tailor the size of each TxFIFO depending on specific buffering requirements.
Page 469: Dma Controller
RM0082 HS_USB 2.0 device In case of a memory access, the DMA transfer engine interfaces with the FIFOs and the AHB interface module of DMA, and indicates to the DMA whether or not the transfer was successful. If the data transfer was unsuccessful, the DMA transfer engine also indicates how many bytes were successfully transferred to the destination, so that the DMA can decide whether to retry the transaction.
Page 470: Theory Of Operation
HS_USB 2.0 device RM0082 23.4 Theory of operation The UDC-AHB Subsystem supports two distinct operation modes: ● DMA mode (detailed in Section 23.4.1), a DMA-based implementation where the UDC- AHB Subsystem acts as an AHB master for data transfers. ● Slave-Only mode (detailed in Section 23.4.2), where the UDC-AHB Subsystem is...
Page 471: Figure 41. Linked-List Memory Structure In Dma Mode
RM0082 HS_USB 2.0 device Figure 41. Linked-list memory structure in DMA mode Setup Buffer Setup buffer Status Quadlet Pointer Data Data OUT Data IN Data Descriptor In buffer Status Quadlet OUT buffer Status Quadlet Descriptor Pointer Pointer Next Pointer Next Pointer Buffer Buffer In buffer Status Quadlet...
Page 472 HS_USB 2.0 device RM0082 USB host. When the transmission is complete, the status is written back into the buffer descriptor’s status quadlet. Then, the subsystem clears the endpoint-specific poll demand bit once the descriptor chain reaches the last descriptor. Note: The application can read the poll demand bit to determine if the descriptor chain is serviced or not.
Page 473: Figure 42. In Transaction Flow In Dma Mode
RM0082 HS_USB 2.0 device Figure 42. In transaction flow in DMA mode Idle Idle Poll demand Transaction Transfer data Data Generate INTR TxFIFO From memory to available? and NAK Availabe? TxFIFO Read the TxFIFO &Provide Packet Service other IN IN data Completely requests and Transferred?
Page 474: Figure 43. Out Transaction Flow In Dma Mode
HS_USB 2.0 device RM0082 Figure 43. Out transaction flow in DMA mode Idle Transaction RxFIFO Send Transfer? available? Write the OUT Data in the Update RxFIFO descriptor status and generate INTR Wait for Status Generate BNA INTR Transfer Enabled? done Got Status Transfer Confirm...
Page 475 RM0082 HS_USB 2.0 device In operation (Data transfer to USB host) If the UDC-AHB subsystem receives an in token from an USB Host for a non-isochronous endpoint (such as, bulk, interrupt or control), it checks the associated TxFIFO (Endpoint FIFO controller (Transmit FIFO controller) on page 467) for data availability.
Page 476: Figure 44. In Transaction Flow In Slave-Only Mode
HS_USB 2.0 device RM0082 Figure 44. In transaction flow in slave-only mode Idle Idle TxFIFO write Transaction Data Generate INTR TxFIFO Retry available? and NAK available? Read the Write data TxFIFO &Provide To TxFIFO IN data TxFIFO full? Transfer done Confirm Packet in TxFIFO Wait for Status...
Page 477: Figure 45. Out Transaction Flow In Slave-Only Mode
RM0082 HS_USB 2.0 device Figure 45. Out transaction flow in slave-only mode Idle Idle Read data from Transaction RxFIFO RxFIFO Send NAK Excess Assert error available? (for non-ISO) read? Write the OUT Transfer done Data in the RxFIFO Wait for Status Got Status Confirm data &...
Page 478: Table 389. Setup Data Memory: Status Quadlet Bit Assignments
HS_USB 2.0 device RM0082 23.5 Data memory structure in DMA mode 23.5.1 SETUP data memory structure The memory structure for SETUP data is given in Figure 46. The 16-byte buffer consists of 4 fields of 32 bits each: the status quadlet (its bit assignments are given in Table 389), a reserved one and the 2 last fields for the 8 bytes of SETUP data.
Page 479: Figure 47. Out Data Memory
RM0082 HS_USB 2.0 device 23.5.2 OUT data memory structure All endpoints that support out direction transactions (that is, endpoints receiving data from the USB Host) must implement a memory structure according to the following characteristics: ● Each data buffer must have an associated descriptor which provides the status of the buffer.
Page 480: Table 390. Out Data Memory: Buffer Status Quadlet Bit Assignments (For Non-Isochronous Out)
HS_USB 2.0 device RM0082 Table 390. Out data memory: buffer status quadlet bit assignments (for Non- Isochronous OUT) Name Description Buffer status. This 2 bit field reports the status of the out buffer, according to encoding: – 2'b00 Host ready. = The descriptor is available to be processed by DMA. [31:30] –...
Page 481: Table 391. Out Data Memory: Buffer Status Quadlet Bit Assignments (For Isochronous Out)
RM0082 HS_USB 2.0 device Table 391. Out data memory: buffer status quadlet bit assignments (for Isochronous OUT) Name Description Buffer status. This 2 bit field reports the status of the out buffer, according to encoding: – 2'b00 Host ready. = The descriptor is available to be processed by DMA. [31:30] –...
Page 482: Figure 48. In Data Memory
HS_USB 2.0 device RM0082 Figure 48. In data memory IN Buffer Status Quadlet Data Descriptor Pointer Reserved Buffer Pointer Next Descriptor Pointer Status Quadlet for Non Iso-chronous IN 31:30 29:28 26:16 15:0 Tx Sts TxBytes Status Quadlet for Iso-chronous IN 15:14 31:30 29:28...
Page 483: Table 393. In Data Memory:buffer Status Quadlet Bit Assignments (For Isochronous)
RM0082 HS_USB 2.0 device Table 393. In data memory:buffer status quadlet bit assignments (for Isochronous) Name Description Buffer status. This 2 bit field reports the status of the in buffer, according to encoding: – 2‘b00, Host ready. The descriptor is available to be processed by DMA. [31:30] –...
Page 484: Operation Modes In Dma Mode
HS_USB 2.0 device RM0082 23.6 Operation modes In DMA mode 23.6.1 Packet-per-buffer mode In packet-per-buffer mode (alternate to buffer fill mode, Buffer fill mode (OUT) on page 484), the DMA transfers packet by packet to various addresses as indicated by the descriptor, implementing then a true scatter-gather mechanism.
Page 485: Burst Split Enable
RM0082 HS_USB 2.0 device is found to be corrupt at the end of the transfer, the descriptor is not updated and the next clean packet overwrites the previous corrupted one. This conceals the USB error from the application. 23.6.5 Burst split enable When burst split is enabled, all AHB transfers (from the DMA to system memory and from system memory to the TxFIFO) are splitted into bursts of a specified length.
Page 486: Table 394. Plug Status Register Bit Assignments
HS_USB 2.0 device RM0082 Table 394. Plug status register bit assignments Name Reset value Description [31:04] Reserved Read: undefined. Write: should be zero. USB PHY mode. This bit allows to set the physical terminations of PHY, according to encoding: [03] phy_mode 1’h1 1‘b0 = Normal (UDC is allowed to drive the USB 2.0...
Page 487: Table 396. In Endpoint-Specific Csrs Summary
RM0082 HS_USB 2.0 device The CSRs can be grouped in two basic categories: ● Global CSRs (listed in Table 398), which are specific to the UDC-AHB subsystem. ● Endpoint CSRs (listed in Table 396 and in Table 397), which are specific to a particular endpoint within the UDC-AHB subsystem.
Page 488: Table 397. Out Endpoint-Specific Csrs Summary
HS_USB 2.0 device RM0082 Table 397. Out endpoint-specific CSRs summary Endpoint Name Offset Type Reset value Control 0x0200 32’h0 Status 0x0204 32’h0 Packet frame number 0x0208 32’h0 Buffer size 0x020C 32’h0 SETUP buffer pointer 0x0210 32’h0 Data description pointer 0x0214 32’h0 Reserved 0x0218...
Page 489: Table 399. Udcl Csrs Summary
RM0082 HS_USB 2.0 device Table 399. UDCl CSRs summary Endpoint Name Offset Type Reset value Reserved 0x0500 UDC20 Endpoint register 0x0504 32’h0 UDC20 Endpoint register 0x0508 32’h0 UDC20 Endpoint register 0x050C 32’h0 UDC20 Endpoint register 0x0510 32’h0 UDC20 Endpoint register 0x0514 32’h0 UDC20 Endpoint register...
Page 490: Table 400. Device Configuration Register Bit Assignments
HS_USB 2.0 device RM0082 Figure 49. UDC-AHB subsystem memory map 32 bit wide Address range 0xE100_0000 Reserved 0xE100_07FF Implemented as 0xE100_0800 RxFIFO 0xE100_0800 RxFIFO depth TxFIFO 0xE110_0000 UDC Subsystem with AHB CSRs 0xE110_04FC 0xE110_0500 UDC CSRs 0xE110_07FC Mamory map (Processor view point) 23.8.3 Register description 23.8.4...
Page 491 RM0082 HS_USB 2.0 device Table 400. Device configuration register bit assignments (continued) Name Reset value Description Reply to USB host Clear_Feature request for endpoint 0. This bit indicates whether the USB device must respond HALT with either a STALL (bit set to 1‘b1) or an ACK (bit set to [16] 1'h0 STATUS...
Page 492: Table 401. Device Control Register Bit Assignments
HS_USB 2.0 device RM0082 Table 400. Device configuration register bit assignments (continued) Name Reset value Description [02] RWKP 1'h0 If set, the USB device is remote wake up capable. Device speed. These 2 bits give the expected speed the application programs for the USB device, according to encoding: –...
Page 493 RM0082 HS_USB 2.0 device Table 401. Device control register bit assignments (continued) Name Reset value Description NAK handshake. setting this bit, the udc-ahb Subsystem returns a NAK [12] DEVNAK 1'h0 handshake to all out endpoints, avoiding then to set the SNAK bit of each endpoint control register (Endpoint control register on page...
Page 494: Table 402. Device Status Register Bit Assignments
HS_USB 2.0 device RM0082 Table 401. Device control register bit assignments (continued) Name Reset value Description DMA receive. [02] 1'h0 Setting this bit, the receive DMA is enabled. [01] Reserved Read: undefined. Write: should be zero. Resuming signaling on the USB. This bit is used by the software application to perform a remote wake-up resume.
Page 495: Device Interrupt Register
RM0082 HS_USB 2.0 device Table 402. Device status register bit assignments (continued) Name Reset value Description Receive FIFO empty status. This bit is set as soon as DMA data transfer has been completed and no new packets have been received. In RXFIFO contrast, this bit is cleared after receiving a valid packet from [15]...
Page 496: Table 403. Device Interrupt Register Bit Assignments
HS_USB 2.0 device RM0082 Note: After checking this register, the application must clear the interrupt by writing a 1‘b1 to the corresponding bit. Table 403. Device interrupt register bit assignments Name Reset value Description [31:07] Reserved Read: undefined. Write: should be zero. Speed enumeration completed.
Page 497: Table 404. Device Interrupt Mask Register Bit Assignments
RM0082 HS_USB 2.0 device 23.8.8 Device interrupt mask register The device interrupt mask is a RW register which allows to mask the system levels interrupts. Setting to 1‘b1 the appropriate bit position in the register the designated interrupt is masked. If masked, the corresponding interrupt signal will not reach the application and its interrupt bit will not be set in the Device Interrupt register (Device interrupt register on page...
Page 498: Table 407. Endpoint Control Register Bit Assignments
HS_USB 2.0 device RM0082 23.8.11 Endpoint control register The endpoint control is an endpoint-specific RW register which allows to setup the endpoint as required by the application. The endpoint control register bit assignments are given in Table 407. Note: If the corresponding endpoint is bidirectional (both in and out), there will be two such endpoint control registers.
Page 499: Endpoint Status Register
RM0082 HS_USB 2.0 device Table 407. Endpoint control register bit assignments (continued) Name Reset value Description Endpoint type. This 2 bit field gives the endpoint type, according to encoding: – 2‘b00 = Control. [05:04] 2’h0 – 2‘b01 = Isochronous (ISO). –...
Page 500: Table 408. Endpoint Status Register Bit Assignments
HS_USB 2.0 device RM0082 Table 408. Endpoint status register bit assignments Name Reset value Description [31:24] Reserved Read: undefined. Isochronous in transaction is completed. This bit indicates that an isochronous (iso) in transaction for this endpoint has been completed. the application can use ISO IN [23] 1'h0...
Page 501: Table 409. Endpoint Buffer Size/Received Packet Frame Number Register Bit Assignments
RM0082 HS_USB 2.0 device Table 408. Endpoint status register bit assignments (continued) Name Reset value Description Out packet reception. This 2 bit field states that if an out packet has been received by the endpoint. The type of the incoming data is given by encoding: –...
Page 502: Endpoint Maximum Packet Size And Buffer Size Register
HS_USB 2.0 device RM0082 Table 409. Endpoint buffer size/received packet frame number register bit assignments (continued) Name Reset value Description Initial data PID to be sent for a high-bandwidth ISO transaction. For IN These 2 bits indicate the initial data PID to be transmitted for an high-bandwidth ISO transaction, according to encoding: –...
Page 503: Table 410. Endpoint Maximum Packet Size/Buffer Size Register Bit Assignments
RM0082 HS_USB 2.0 device Table 410. Endpoint maximum packet size/buffer size register bit assignments Name Reset value Description Buffer size required for this endpoint. This 16 bit field represent the size of the buffer in the RxFIFO associated to that out endpoint as an integer [31:16] BUFF SIZE 16’h0000...
Page 504 HS_USB 2.0 device RM0082 Table 413. Endpoint register bit assignments (continued) Name Reset value Description [10:07] ConfNumber 4’h0 Configuration number to which this endpoint belongs. Endpoint type. The possible options are: – 2’b00: Control [06:05] EPType 2’h0 – 2’b01: Isochronous –...
Page 505: Overview
RM0082 HS_Media independent interface (MII) HS_Media independent interface (MII) 24.1 Overview Within its high-speed (HS) connection subsystem, the device provides an Ethernet MAC 10/100 Universal (commonly referred as MAC-UNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard. In particular, MAC-UNIV in the device is configured to offer an AHB-interfaced native DMA (also referred as MAC-AHB) over a MAC core.
Page 506: Figure 50. Mac-Univ (Mac-Ahb Configuration) System-Level Block Diagram
HS_Media independent interface (MII) RM0082 Figure 50. MAC-UNIV (MAC-AHB configuration) system-level block diagram TxFIFO RxFIFO (Mem) (Mem) Master TxFC RxFC Interface Register Slave Interface MAC-CORE MAC-MTL MAC-DMA MAC-AHB 24.3 Main functions description 24.3.1 AHB slave interface The AHB Slave Interface block allows the host CPU to access all the DMA and MAC control and status registers (CSRs).
Page 507: Dma Controller
RM0082 HS_Media independent interface (MII) 24.3.3 DMA controller A native DMA is available within the MAC-AHB, and its DMA controller interfaces both with the host through the AHB interface and with the MAC core (Section 24.1.1). The DMA controller has Independent Transmit and Receive engines. The Transmit Engine transfers data from system memory (through the AHB master interface) to MAC core, while the Receive Engine transfers data from the MAC core to the system memory (through AHB master interface).
Page 508: Power Management Module (Pmt)
HS_Media independent interface (MII) RM0082 24.3.6 Power management module (PMT) This section describes the power management (PMT) mechanism as supported by the MAC. PMT supports the reception of network (remote) wake-up frames and Magic Packet frames. PMT does not perform the clock gate function, but generates interrupts for wake-up frames and Magic Packets received by the MAC.
Page 509: Figure 51. Dma Descriptor List: Ring Structure (Left) And Chain Structure (Right)
RM0082 HS_Media independent interface (MII) Figure 51. DMA descriptor list: ring structure (left) and chain structure (right). Buffer 1 Buffer 1 Descriptor 0 Descriptor 0 Buffer 2 Buffer 1 Descriptor 1 Buffer 2 Buffer 1 Descriptor 1 Buffer 1 Descriptor 2 Buffer 2 Buffer 1 Descriptor 2...
Page 510: Table 414. Transmit Descriptor 0 (Tdes0)
HS_Media independent interface (MII) RM0082 Figure 52. DMA descriptor format (Transmit Descriptor, 32 bit) Ctrl Reserved Ctrl Reserved Status [16:0] TDES0 [30:26] [25:24] [23:20] [19:17] Reserved Reserved Buffer 2 Byte Count Buffer 2 Byte Count TDES1 [31:29] [15:13] [28:16] [12:0] Buffer 1 Address [31:0] TDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0]...
Page 511 RM0082 HS_Media independent interface (MII) Table 414. Transmit descriptor 0 (TDES0) (continued) Name Description When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When [20] TDES0[20] is set, TBS2 (TDES1[28:16]) is a "don't care" value. TDES0[21] takes precedence over TDES0[20].
Page 512: Table 415. Transmit Descriptor 1 (Teds1)
HS_Media independent interface (MII) RM0082 Table 414. Transmit descriptor 0 (TDES0) (continued) Name Description Excessive Deferral. If set, it indicates that the transmission has ended because of excessive deferral of over 24288 bit times (155680 bit times in [02] Jumbo Frame Enabled Mode), if the DC (Deferral Check) bit in the MAC Configuration register (Register 0) is set.
Page 513: Table 418. Receive Descriptor 0 (Rdes0)
RM0082 HS_Media independent interface (MII) 24.4.2 Receive descriptors As for Transmit Descriptors above, there are four different Receive Descriptors: ● Receive descriptor 0, RDES0 (Table 418): it contains the status of the received frame, the frame length and the descriptor ownership information. ●...
Page 514: Table 419. Receive Descriptor 1 (Rdes1)
HS_Media independent interface (MII) RM0082 Table 418. Receive descriptor 0 (RDES0) (continued) Name Description Overflow Error. If set, it indicates that received frame was damaged due to [11] buffer overflow in MAC core. Van Tag. If set, it indicates that the frame pointed to by this descriptor is a [10] VLAN VLAN frame tagged by the MAC core.
Page 515: Table 420. Receive Descriptor 2 (Rdes2)
RM0082 HS_Media independent interface (MII) Table 419. Receive descriptor 1 (RDES1) (continued) Name Description [13] Reserved Receive Buffer 1 Size. These 11 bit field reports the size (in bytes) of the first data buffer. Note: The RBS1 value must be a multiple of 4/8/16 depending on the bus [12:00] RBS1 width otherwise the resulting behaviour is undefined.
Page 516: Figure 54. Interrupt Management: Sbd_Intr_O And Pmt_Intr_O Generation
HS_Media independent interface (MII) RM0082 24.6 Interrupt management Figure 54. Interrupt management: sbd_intr_o and pmt_intr_o generation pmt_intr_o PMT_INTR ~PMT_INTR_MASK To VIC IRQ 55 MMC_INTR sbd_intr_o To VIC IRQ 56 Note:Signals NIS and AIS are registered The Ethernet MAC provides two interrupt lines to VIC (Vectored Interrupt Controller): ●...
Page 517: Table 422. Mac-Univ Dma Registers Summary
RM0082 HS_Media independent interface (MII) 24.7 Programming model 24.7.1 Register map The MAC-UNIV can be fully configured by programming a set of 32 bit wide registers which can be accessed at the base address 0xE080_0000. The MAC-UNIV registers can be grouped in two different classes: ●...
Page 518: Table 424. Mmc (Mac Management Counters) Registers
HS_Media independent interface (MII) RM0082 Table 423. MAC-UNIV MAC global registers summary (continued) Name Offset Reset value Description Register 8 0x0020 8’h10 Version Register (RO). 0x0024 Reserved. Register 10 0x0028 Pointer To Wake-up Frame Filter Registers. Register 11 0x002C 32’h0 Pmt Control And Status Register.
Page 519 RM0082 HS_Media independent interface (MII) Table 424. MMC (MAC management counters) registers (continued) Name Offset Reset Value Description Txbroadcastframes_g is the number of good broadcast Register 71 0x011C 32’h0 frames transmitted Txmulticastframes_g is the number of good multicast Register 72 0x0120 32’h0 frames transmitted...
Page 520 HS_Media independent interface (MII) RM0082 Table 424. MMC (MAC management counters) registers (continued) Name Offset Reset Value Description Txcarriererror is the number of frames aborted due to Register 88 0x0160 32’h0 carrier sense error (no carrier or loss of carrier). Txoctetcount_g is the number of bytes transmitted, Register 89 0x0164...
Page 521: Register Description
RM0082 HS_Media independent interface (MII) Table 424. MMC (MAC management counters) registers (continued) Name Offset Reset Value Description Rx64octects_gb is the number of good and bad frames Register 107 0x01AC 32’h0 received with length 64 bytes, exclusive of preamble. Rx65to127octects_gb is the number of good and bad Register 108 0x01B0 32’h0...
Page 522: Table 425. Bus Mode Register Bit Assignments
HS_Media independent interface (MII) RM0082 Table 425. Bus mode register bit assignments Name Reset Value Type Description [31:17] Reserved Read: undefined [16] 1’h0 Fixed Burst [15:14] 2’h0 Rx:Tx Priority Ratio. [13:08] 6’h0 Programmable Burst Length. [07] Reserved Read: undefined [06:02] 5’h0 Descriptor Skip Length.
Page 523: Table 426. Transmit Poll Demand Register Bit Assignments
RM0082 HS_Media independent interface (MII) VALUE ARBITRATION SCHEME 1‘b0 Round robin with Rx:Tx priority given in PR field. 1‘b1 Rx has priority over Tx. ● Setting this bit, the DMA Controller resets all MAC internal registers and logic. This bit is automatically cleared after the reset has completed.
Page 524: Table 428. Receive Descriptor List Address Register Bit Assignments
HS_Media independent interface (MII) RM0082 Note: Writing to this register is permitted only when reception is stopped. When stopped, the register must be written to before the receive Start command is given. Table 428. Receive descriptor list address register bit assignments Name Reset value Type Description...
Page 525: Table 430. Status Register Bit Assignments
RM0082 HS_Media independent interface (MII) Table 430. Status register bit assignments Name Reset Value Type Description [31:29] Reserved Read:undefined [28] 1’h0 MAC PMT Interrupt [27] 1’h0 MAC MMC Interrupt [26] Reserved Read:undefined [25:23] 3’h0 Error bits [22:20] 3’h0 Transmit Process State. [19:17] 3’h0 Receive Process State.
Page 526: Table 431. Eb Field Bit Assignments
HS_Media independent interface (MII) RM0082 Table 431. EB field bit assignments Bit 23 Bit 24 Bit 25 Error 1‘b0 During data transfer by RxDMA. 1‘b1 During data transfer by TxDMA. 1‘b0 During write transfer. 1‘b1 During read transfer. 1‘b0 During data buffer access. 1‘b1 During descriptor access.
Page 527: Table 433. Rs Field Bit Assignments
RM0082 HS_Media independent interface (MII) Table 433. RS field bit assignments Value State Description 3‘b000 Stopped Reset or stop reception command issued. 3‘b001 Running Fetching receive transfer descriptor. 3‘b010 Reserved 3‘b011 Running Waiting for receive packet. 3‘b100 Suspended Receive descriptor unavailable. 3‘b101 Running Closing receiving descriptor.
Page 528 HS_Media independent interface (MII) RM0082 Table 435. AIS field bit assignments (continued) Field Early Transmit Interrupt Fatal Bus Error Note: This bit must be cleared (writing a 1'b1) each time a corresponding bit that causes AIS to be set is cleared. ●...
Page 529: Operation Mode Register (Register 6, Dma)
RM0082 HS_Media independent interface (MII) suspended. This bit is set only when the previous descriptor in Receive list is owned by DMA. ● If set it indicates the completion of frame reception. Note that Receive Process remains in running state. ●...
Page 530: Table 436. Operation Mode Register Bit Assignments
HS_Media independent interface (MII) RM0082 Table 436. Operation mode register bit assignments Name Reset Value Type Description [31:22] Reserved Read: undefined [21] 1’h0 Store and Forward. [20] 1’h0 Flush Transmit FIFO. [19:17] Reserved Read: undefined. [16:14] 3’h0 Transmit Threshold Control. [13] 1’h0 Start/Stop Transmission Command.
Page 531: Table 438. Rfd Field Bit Assignments
RM0082 HS_Media independent interface (MII) Table 437. TTC field bit assignments (continued) Value Threshold (Byte) 3‘b110 3‘b111 Note: This field is used only when SF bit in this register is cleared. ● Setting this bit, the transmission process is placed in the Running state, and the DMA checks the Transmit List for a frame to be transmitted either at the current position (pointed by the Transmit Descriptor List Address register, Section...
Page 532: Table 440. Rtc Field Bit Assignments
HS_Media independent interface (MII) RM0082 Note: This bit is not used (reserved) when the Receive FIFO size is less than 4Kbytes. ● Setting this bit, all frames except runt-error frames will be forwarded to the DMA. Otherwise, the Receive FIFO will drop frames with error status. ●...
Page 533: Table 442. Missed Frame And Buffer Overflow Counter Register Bit Assignments
RM0082 HS_Media independent interface (MII) Table 441. Interrupt enable register bit assignments (continued) Name Reset value Type Description [13] 1’h0 Fatal bus error interrupt enable. [12:11] Reserved Read: undefined. [10] 1’h0 Early transmit interrupt enable. [09] 1’h0 Receive watchdog timeout enable. [08] 1’h0 Receive stopped enable.
Page 534: Current Host Receive Descriptor Register (Register19, Dma)
HS_Media independent interface (MII) RM0082 24.7.13 Current host receive descriptor register (Register19, DMA) The Current Host Receive Descriptor is a RO register which points to the start address of the current receive descriptor read by the DMA. This pointer is updated by DMA during operation.
Page 535: Table 443. Mac Configuration Register Bit Assignments
RM0082 HS_Media independent interface (MII) Table 443. MAC configuration register bit assignments Name Reset Value Type Description [31:24] Reserved Read: undefined [23] 1’h0 Watchdog Disable. [22] 1’h0 Jabber Disable. [21] Reserved Read: undefined. [20] 1’h0 Jumbo Frame Enable. [19:17] 3’h0 Inter Frame Gap.
Page 536: Table 444. Ifg Field Bit Assignments
HS_Media independent interface (MII) RM0082 Table 444. IFG field bit assignments Value Inter Frame Gap 3‘b000 96 bit times 3‘b001 88 bit times 3‘b010 80 bit times 3‘b111 40 bit times Note: In half-duplex mode, the minimum IFG can be configured up to 64 bit times (IFG = 3'b100). ●...
Page 537: Table 445. Bl Field Bit Assignments
RM0082 HS_Media independent interface (MII) field greater than or equal to 1501 bytes will be passed to the application without stripping the Pad/FCS field. Clearing this bit, the MAC will pass unmodified all incoming frames to the application. ● This 2 bit field represents the back-off limit which determines the random integer number (r) of slot time delays (that is., 512 bit times) the MAC waits before rescheduling a transmission attempt during retries after a collision.
Page 538: Table 446. Mac Frame Filter Register Bit Assignments
HS_Media independent interface (MII) RM0082 Table 446. MAC frame filter register bit assignments Name Reset Value Type Description [31] 1’h0 Receive All. [30:11] Reserved Read: undefined [10] 1’b0 Hash or Perfect Filter [09] 1’h0 Source Address Filter Enable. [08] SAIF 1’h0 SA Inverse Filtering.
Page 539: Table 447. Pcf Field Bit Assignments
RM0082 HS_Media independent interface (MII) Table 447. PCF field bit assignments Value Description 2‘b00 MAC filters all control frames from reaching application 2‘b01 2‘b10 MAC forwards all control frames to application even if they fail the address filter. 2‘b11 MAC forwards all control frames that pass the address filter. ●...
Page 540: Table 448. Mii Address Register Bit Assignments
HS_Media independent interface (MII) RM0082 24.7.20 MII address register (Register4, MAC) The MII Address is a register which controls the management cycles to the external PHY through the management interface. The MII address bit assignments are given in Table 448. Table 448.
Page 541: Table 449. Cr Field Bit Assignments
RM0082 HS_Media independent interface (MII) Table 449. CR field bit assignments Value CSR Frequency Range MDC Clock 3‘b000 60-100 MHz CSR clock/42 3‘b001 100-150 MHz CSR clock/62 3‘b010 20-35 MHz CSR clock/16 3‘b011 35-60 MHz CSR clock/26 3‘b100 150-250 MHz CSR clock/102 3‘b101 250-300 MHz...
Page 542: Table 451. Flow Control Register Bit Assignments
HS_Media independent interface (MII) RM0082 Table 451. Flow control register bit assignments Name Reset Value Type Description [31:16] 16’h0 Pause Time. [15:08] Reserved Read: undefined. DZPQ 1’b0 Disable Zero-Quanta Pause Reserved Read: undefined [05:04] 2’h0 Pause Low Threshold. [03] 1’h0 Unicast Pause Frame Detect.
Page 543: Table 453. Vlan Tag Register Bit Assignments
RM0082 HS_Media independent interface (MII) register (1.4.2.25), in addition to the detecting Pause frame with the unique multicast address. Clearing this bit, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard. ●...
Page 544: Table 454. 4 Bit Command Registers
HS_Media independent interface (MII) RM0082 Figure 55. Wake-up frame filter registers wkupfmfilter_reg0 Filter 0 Byte Mask wkupfmfilter_reg0 Filter 1 Byte Mask Filter 2 Byte Mask wkupfmfilter_reg0 Filter 3 Byte Mask wkupfmfilter_reg0 Filter 3 Filter 1 Filter 0 Filter 2 RSVD RSVD wkupfmfilter_reg0 RSVD...
Page 545: Table 455. Pmt Csr Bit Assignments
RM0082 HS_Media independent interface (MII) Table 455. PMT CSR bit assignments Reset value Type Description Wake-up frame filter register pointer reset. If set, it resets the remote wake-up frame filter pointer to 3’b000 [31] 1’h0 (eight remote wake-up registers are present). It is automatically cleared after 1 clock cycle.
Page 546: Table 457. Interrupt Mask Register Bit Assignments
HS_Media independent interface (MII) RM0082 Table 456. Interrupt status register bit assignments (continued) Reset Value Type Description MMC Interrupt Status This bit is set high whenever an interrupt is generated in the MMC [04] 1’h0 Interrupt register (see section MMC Receive Interrupt Register). This bit is cleared whenever the bit in the interrupt register is cleared.
Page 547: Table 459. Mac Address0 Low Register Bit Assignments
RM0082 HS_Media independent interface (MII) Table 459. MAC Address0 low register bit assignments Name Reset value Type Description [31:00] A[31:0] 32’hFFFFFFFF MAC address0 [31:00]. 24.7.30 MAC address1 high register (Register18, MAC) The MAC Address1 High is a register which contains the upper 16 bits ([47:32]) of the 6-byte MAC address of the station.
Page 548: Table 462. Mac Address1 Low Register Bit Assignments
HS_Media independent interface (MII) RM0082 24.7.31 MAC address1 low register (Register19, MAC) The MAC Address1 Low is a register which contains the lower 32 bits ([31:0]) of the 6-byte MAC address of the station. The MAC address1 Low bit assignments are given in Table 462.
Page 549: Table 464. Mmc Receive Interrupt Register Bit Assignments
RM0082 HS_Media independent interface (MII) Table 463. MMC control register bit assignments (continued) Name Reset value Type Description Counter stop rollover. When set, counter after reaching [01] 1’h0 maximum value will not roll over to zero. Counters reset. When set, all counters will be reset. This [00] 1’h0 bit will be cleared automatically after 1 clock cycle.
Page 550: Table 465. Mmc Transmit Interrupt Register Bit Assignments
HS_Media independent interface (MII) RM0082 Table 464. MMC receive interrupt register bit assignments (continued) Name Reset value Type Description The bit is set when the rxoversize_g counter [10] 1’h0 reaches half the maximum value. The bit is set when the rxundersize_g counter [09] 1’h0 reaches half the maximum value.
Page 551 RM0082 HS_Media independent interface (MII) Table 465. MMC transmit interrupt register bit assignments (continued) Name Reset value Type Description The bit is set when the txoctectcount_g counter reaches [20] 1’h0 half the maximum value. The bit is set when the txcarriererror counter reaches [19] 1’h0 half the maximum value.
Page 552: Table 466. Mmc Receive Interrupt Mask Register Bit Assignments
HS_Media independent interface (MII) RM0082 24.8.4 MMC receive interrupt mask register The MMC receive interrupt mask register maintains masks for the interrupts generated when receive statistic counters reach half their maximum values. (MSB of the counters is set.) It is a 32 bit wide register. Table 466.
Page 553: Clocks With Mii
RM0082 HS_Media independent interface (MII) Table 466. MMC receive interrupt mask register bit assignments (continued) Name Reset value Type Description The bit is set when the rx128to255octects_gb counter [06] 1’h0 reaches half the maximum value. The bit is set when the rx65to127octects_gb counter [05] 1’h0 reaches half the maximum value.
Page 554: Figure 56. Clocking Scheme For Mac-Ahb
HS_Media independent interface (MII) RM0082 Figure 56. Clocking scheme for MAC-AHB 554/844 Doc ID 018672 Rev 1...
Page 555: Table 467. Gpio Signal Interface
RM0082 LS_JPEG codec LS_JPEG codec 25.1 Overview Within its Low Speed Connectivity Block, the device provides a JPEG Codec with header processing which is built around existing JPEG ECS CODEC and extends its functionality by providing additional support for JPEG Header parsing and generation. The encoding process compresses 8x8 pixel blocks (data units) into either a complete JPEG encoded output stream or only ECS data depending on whether the header processing functionality of the core is enabled.
Page 556: Figure 57. Jpgc Signal Interfaces Diagram
LS_JPEG codec RM0082 Figure 57. JPGC signal interfaces diagram AHB Slave JPEG Codec AHB Master DMAC 25.3 Functional description 25.3.1 Block diagram The block diagram of the JPGC is shown in Figure Figure 58. JPGC block diagram A H B M a s te r D M A C A H B S la v e C O D E C...
Page 557: Main Functions Description
RM0082 LS_JPEG codec 25.3.2 Main functions description As one can see from the block diagram (Figure 58), the main building blocks of the JPGC are five: ● The Codec Core; ● The Codec Controller; ● The DMA controller (DMAC); ● The FIFO buffers (FIFO in and FIFO out);...
Page 558: Table 468. Jpgc Memory Map
LS_JPEG codec RM0082 correct transfer parameters, before any coding process can start. See also Chapter 19: BS_DMA controller, for an in-depth description of the direct memory access block. 25.3.6 FIFO buffers These two First-in First-out buffers have a word width of 32 bits, and a depth of 8 words. FIFO’s are used by the Codec Controller to bufferize the flow of data incoming to (FIFO In) and outcoming from (FIFO out) the Codec Core.
Page 559: Table 469. Jpgc Codec Core Registers
RM0082 LS_JPEG codec Table 468. JPGC memory map (continued) Name Base address HuffBase Memory 0x1000 HuffSymb Memory 0x1400 DHTMem Memory 0x1800 HuffEnc Memory 0x1C00 Table 469. JPGC codec core registers Name Offset Type Reset value Description JPGCReg0 0x00 32’h0 Codec Core Register 0 JPGCReg1 0x04 32’h0...
Page 560: Table 472. Jpgc Internal Memories
LS_JPEG codec RM0082 Table 472. JPGC internal memories Reset Name Offset Type Description value JPGCQMem 0x0800 Quantization Table Memory. JPGCHuffMin 0x0C00 Huffmin Table Memory. JPGCHuffBase 0x1000 Huffbase Table Memory. JPGCHuffSymb 0x1400 Huffsymb Table Memory. JPGCDHTMem 0x1800 Dht Marker Segment Memory. JPGCHuffEnc 0x1C00 Huffenc Table Memory.
Page 561: Table 474. Jpgcreg1 Register Bit Assignments
RM0082 LS_JPEG codec Table 474. JPGCreg1 register bit assignments Reset Name Description Value [31:16] Ysiz Number of lines. [15:09] Reserved [08] Header processing enable. Number of components for scan header marker segment minus [07:06] [05:04] colspctype Number of quantization tables in the output stream. [03] Decoding/encoding.
Page 562: Table 475. Jpgcreg2 Register Bit Assignments
LS_JPEG codec RM0082 Table 475. JPGCreg2 register bit assignments Reset Name Description Value [31:26] Reserved [25:00] NMCU Number of MCU’s minus 1. ● NMCU This value defines the number of minimum coded units to be coded, minus 1; there can be from 0 to 67,108,863 MCU’s.
Page 563: Table 477. Jpgcreg4-7 Register Bit Assignments
RM0082 LS_JPEG codec Table 477. JPGCreg4-7 register bit assignments Reset Name Description Value [31:16] Reserved [15:12] Vertical sampling factor for component i. [11:08] Horizontal sampling factor for component i. Number of data units of the component I contained in a MCU, [07:04] Nblocki minus 1.
Page 564: Table 478. Jpgc Control Status Register Bit Assignments
LS_JPEG codec RM0082 Table 478. JPGC control status register bit assignments Reset Name Description value [31] End of Conversion (Active High) Synchronous Core Reset (Active High). Write only field. Writing 1 [30] on this bit will reset & disable both CODEC and controller. Clear this bit to enable CODEC.
Page 565: Table 480. Jpgc Bytes From Core To Fifo Register Bit Assignments
RM0082 LS_JPEG codec 25.4.10 JPGC bytes from core to Fifo register This register contains the number of bytes that have been sent, at a given time, from the codec core to the FIFO Out buffer. The content of this register is cleared automatically when a new coding process starts.
Page 566: Table 482. Jpgc Fifo In Register Bit Assignments
LS_JPEG codec RM0082 Table 482. JPGC Fifo in register bit assignments Reset Name Description Value [31:00] DATA FIFO data. ● DATA Data read from, or written to, the FIFO In buffer. 25.4.14 JPGCFifoOut register This register is used to read data from, or write data to, the FIFO out, which is used to bufferize the transfers from the codec core to the external RAM, under the control of the codec controller.
Page 567: Table 485. Jpgchuffmin Memory Map
RM0082 LS_JPEG codec 25.4.16 JPGChuffmin memory Together with the HuffBase table and the HuffSymb table, this is one of the three Huffman tables required by the Codec Core when it acts as a decoder. The HuffMin table can be up to 4 x 100 bit words. its memory map is shown in Table 485.
Page 568: Table 488. Jpgcdhtmem Memory Map
LS_JPEG codec RM0082 Table 487. JPGC huffsymb memory map (continued) First address Last address Table SYMB DC 0 and 1values SYMB AC 1 value When decoding with header processing, this table is automatically programmed by the codec core, while in the case of ECS only decoding, the HuffSymb table must be programmed before starting the codec core.
Page 569: Table 489. Jpgchuffenc Memory Map
RM0082 LS_JPEG codec Table 489. JPGCHuffEnc memory map First address Last address Table AC Huffman table 0 AC Huffman table 1 DC Huffman table 0 DC Huffman table 1 Each AC table requires 176 x 12 bit words. Each DC table requires 16 x 12 bit words. All the AC and DC tables occupy contiguous locations in the JPGCHuffEnc memory.
Page 570: Table 491. Location Of Dc Huffman Codes In Jpgchuffenc Memory
LS_JPEG codec RM0082 Table 490. Location of AC huffman codes in JPGCHuffEnc memory (continued) Address Value 140-149 Huffman code of run lengths E/1 to E/A 150-159 Huffman code of run lengths F/1 to F/A Huffman code of EOB Huffman code of ZRL 162-167 $FFF 168-175...
Page 571: Overview
RM0082 LS_Fast IrDA controller LS_Fast IrDA controller 26.1 Overview Within its low speed connectivity subsystem, the device provides a fast IrDA Controller modeled according to the standard of the infrared data association (IrDA). It is a programmable infrared controller that acts as an interface between the on-chip AHB bus and infrared transceiver.
Page 572: Figure 59. Dataflow Block Diagram Of The Firda Controller
LS_Fast IrDA controller RM0082 Figure 59. Dataflow block diagram of the FIrDA controller TX Signal RX Signal Fast IRDA Interface Synchronization Unit Modulation Unit Demodulation Unit RX Frame TX Frame En_symb En_pulse Wrapper Unit Baud Generation Unit Irda_clk Synchronization bus_clk FIFO Unit Bus interface Status &...
Page 573: Demodulation Unit
RM0082 LS_Fast IrDA controller reset the bit RXS of the IrDA_STAT register. At last, a frame invalid interrupt (FI_INT, Section 26.4) is generated. This behaviour allows to handle the case of a frame abort. Note: The used reception abort timer has to be programmed via the field RATV of the configuration register IrDA_CONF (Section 26.5.5).
Page 574: Modulation Unit
LS_Fast IrDA controller RM0082 26.3.4 Modulation unit The modulation unit is active in the transmission state only, and it is responsible for the modulation of the TX frames from the wrapper unit in order to generate the TX signal for the off-chip IrDA transceiver.
Page 575: Table 492. Settings Of K,L And (N+1) Parameters For Sir,Mir And Fir In Baud Rate Generation Unit
RM0082 LS_Fast IrDA controller duration for FIR transmission (like MIR), the baud rate generation unit has to create a pulse rate of fen_pulse = 4* f en_symb Table 492 provides a list of the settings of K, L and (N+1) parameters in case of SIR, MIR and FIR (and with f = 48 MHz).
Page 576 LS_Fast IrDA controller RM0082 controller, respectively. The burst size is programmable by the field BS of IrDA_CONF register (Section 26.5.5). Transmission state In order to start to transmit data, the software writes the frame size to the 12 bit field TFS of transmission frame size register (IrDA_TFS, Section 26.5.9).
Page 577: Table 494. Firda Controller Interrupt Summary
RM0082 LS_Fast IrDA controller When the received frame has been completely read out of the buffer, the FIrDA controller changes back to the listening stage. 26.4 Interrupt sources Table 494 shows a summary of the interrupts of the FIrDA controller. A brief description of each interrupt follows after the table.
Page 578: Table 496. Firda Controller Control And Status Registers Summary
LS_Fast IrDA controller RM0082 26.5 Programming model 26.5.1 External pin connection Table 495. External pin connection Signal Ball IrDA_RXD IrDA_TXD 26.5.2 Register map The FIrDA controller can be fully configured by programming its 32 bit wide registers which can be accessed at the base address 0xD100_0000. As depicted in Figure 59, FIrDA controller registers can be logically arranged in three main...
Page 579: Table 499. Irda_Con Register Bit Assignments
RM0082 LS_Fast IrDA controller Table 498. FIrDA controller interrupt and DMA registers summary (continued) Name Offset Type Reset value Description IrDA_ICR 0xF4 32’h0 Interrupt clear. IrDA_ISR 0xF8 32’h0 Interrupt set. IrDA_DMA 0xFC 32’h0 DMA control. 26.5.3 Register description 26.5.4 IrDA_CON register The IrDA_CON (control) is a RW register which allows to control the FIrDA controller.
Page 580: Irda_Para Register
LS_Fast IrDA controller RM0082 Table 500. IrDA_CONF register bit assignments (continued) Name Reset value Description Burst size. This 3 bit field indicates the value of the burst size, according to the encoding: – 3‘b000 = 1 word [18:16] 3’h2 – 3‘b001 = 2 words –...
Page 581: Table 501. Irda_Para Register Bit Assignments
RM0082 LS_Fast IrDA controller Table 501. IrDA_PARA register bit assignments Name Reset value Description [31:28] Reserved Read: undefined. Write: should be zero. Maximum number of received bytes. This 12 bit field indicates the maximum number of received bytes, according to the encoding: –...
Page 582: Table 502. Irda_Dv Register Bit Assignments
LS_Fast IrDA controller RM0082 Table 502. IrDA_DV register bit assignments Name Reset value Description [31:27] Reserved Read: undefined. Write: should be zero. Decrement value of fractional divider. This 11 bit field represents the decrement value of the [26:16] 11’h0 fractional divider, following the formula DEC = L – K, where L and K values are listed in Table 492.
Page 583: Table 504. Irda_Tfs Register Bit Assignments
RM0082 LS_Fast IrDA controller Table 504. IrDA_TFS register bit assignments Name Reset value Description [31:12] Reserved Write: should be zero. Transmission frame size. This 12 bit field indicates the size of the transmitted frame, according to the encoding: – 12‘b000000000000 = Reset value. –...
Page 584: Table 506. Irda_Txb Register Bit Assignments
LS_Fast IrDA controller RM0082 Table 506. IrDA_TXB register bit assignments Name Reset value Description [31:00] 32’h0 Transmission data. Note: Between two write accesses there must be a pause of one clock cycle. 26.5.12 IrDA_RXB register The IrDA_RXB (reception buffer) is a RO register which contains the receive data bytes in reception mode.
Page 585: Table 509. Irda_Ris Register Bit Assignments
RM0082 LS_Fast IrDA controller Table 509. IrDA_RIS register bit assignments Name Reset value Description Read: undefined. [31:08] Reserved 1‘b0 = No interrupt. 1‘b1 = Interrupt pending. Frame detected raw interrupt status. [07] 1’h0 1‘b0 = No interrupt. 1‘b1 = Interrupt pending. Frame invalid raw interrupt status.
Page 586: Table 510. Irda_Mis Register Bit Assignments
LS_Fast IrDA controller RM0082 Table 510. IrDA_MIS register bit assignments Name Reset value Description Read: undefined. Write: should be zero. [31:08] Reserved 1‘b0 = No interrupt. 1‘b1 = Interrupt pending. Frame detected masked interrupt status. [07] 1’h0 1‘b0 = No interrupt. 1‘b1 = Interrupt pending.
Page 587: Table 512. Irda_Isr Register Bit Assignments
RM0082 LS_Fast IrDA controller Table 511. IrDA_ICR register bit assignments (continued) Name Reset value Description [04] 1’h0 Frame transmitted interrupt clear. [03] BREQ 1’h0 BREQ interrupt clear. [02] LBREQ 1’h0 LBREQ interrupt clear. [01] SREQ 1’h0 SREQ interrupt clear. [00] LSREQ 1’h0 LSREQ interrupt clear.
Page 588 LS_Fast IrDA controller RM0082 Table 513. IrDA_DMA register bit assignments (continued) Name Reset value Description [01] SREQEN 1’h0 Single request DMA enable. [00] LSREQEN 1’h0 Last single request DMA enable. 588/844 Doc ID 018672 Rev 1...
Page 589: Overview
LS_Universal asynchronous receiver/transmitter (UART) 27.1 Overview SPEAr300 has single UART: ● UART has a maximum baud rate of 3 Mbps and minimum baud rate of 45 bps. It supports modem control and hardware flow control signals. Each UART is intended to perform: ●...
Page 590: Figure 60. Uart Block Diagram
LS_Universal asynchronous receiver/transmitter (UART) RM0082 27.2 Functional description 27.2.1 Block diagram Figure 60. UART block diagram Read data[11:0] rxd[11:0] nUARTRST Write data[7:0] 16x8 16x12 Transmit Receive FIFO FIFO txd[7:0] PCLK PRESETn PSEL Control and status UARTTXD Transmitter Baud rate divisor PENABLE Baud16 APB interface...
Page 591 RM0082 LS_Universal asynchronous receiver/transmitter (UART) Baud Rate Generator The Baud Rate Generator contains free-running counters that generate the internal x16 clocks, and Baud16 signal. Baud16 provides timing information for UART transmit and receive control. It consists of a stream of pulses with a width of one UARTCLK clock period and a frequency of 16 times the baud rate.
Page 592: Table 514. Uart Interrupt Summary Together With Combined Outputs
LS_Universal asynchronous receiver/transmitter (UART) RM0082 both FIFO’s act like a one-byte holding register), only the DMA single transfer mode can operate, since only one character can be transferred to or from the FIFO at any time. Synchronization registers and logic Since the UART supports both asynchronous and synchronous operation of the clocks PCLK and UARTCLK, Synchronization Registers and Handshaking Logic have been implemented and are active at all times.
Page 593 RM0082 LS_Universal asynchronous receiver/transmitter (UART) UARTRXINTR ● This interrupt is asserted when one of the following events occurs: ● If the FIFOs are enabled and the Receive FIFO reaches the programmed trigger level. ● The interrupt is then cleared by reading data from the Receive FIFO until it becomes less than the trigger level, or by clearing the interrupt;...
Page 594: Table 515. Uart Base Address
LS_Universal asynchronous receiver/transmitter (UART) RM0082 27.3 Programming model 27.3.1 Register map The UART can be fully configured by programming its registers which can be accessed at the base address shown in Table 515: UART base address. Table 515. UART base address UART Base Address UART...
Page 595: Table 519. Uart Interrupts And Dma Registers Summary
RM0082 LS_Universal asynchronous receiver/transmitter (UART) Table 518. UART control and status register summary (continued) Name Offset Width(bit) Type Reset value Description UARTFBRD 0x028 6‘h0 Fractional baud rate. UARTLCR_H 0x02C 16‘h0 Line control. UARTCR 0x030 16‘h0300 UART control. Note: UARTLCR_H, UARTIBRD and UARTFBRD form a single 30 bit wide register named UARTLCR, which is updated on a single write strobe generated by a UARTLCR_H write.
Page 596: Table 521. Uart Data Register Summary
LS_Universal asynchronous receiver/transmitter (UART) RM0082 register (bottom word of the transmit FIFO). The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the parity bit (if enabled) and a stop bit. The resultant word is then transmitted. For received words, if FIFOs are enabled, the data byte and the 4 bit status (break, frame, parity and overrun) is pushed into the 12 bit receive FIFO.
Page 597: Table 524. Uartfr Register Bit Assignments
RM0082 LS_Universal asynchronous receiver/transmitter (UART) 27.4.3 UARTFR register The UARTFR (flag) is a RO register which indicates the flag status. The UARTFR bit assignments are given in Table 524. Table 524. UARTFR register bit assignments Name Reset value Description [15:09] Reserved Read: as zero.
Page 598: Table 525. Uartibrd Register Bit Assignments
LS_Universal asynchronous receiver/transmitter (UART) RM0082 Table 524. UARTFR register bit assignments (continued) Name Reset value Description Data set ready. This bit is set to 1‘b1 when the modem status input is 1‘b0 [01] 1’h0 (Section 27.5). Specifically, it is the complement of the UART data carrier detect nUARTDSR modem status input.
Page 599: Table 527. Typical Baud Rate And Divisors
RM0082 LS_Universal asynchronous receiver/transmitter (UART) Table 527. Typical baud rate and divisors Programmed integer divisor Bit rate [Bps] Error (UARTIBRD) 16‘h000D 230400 0.16% 16‘h001A 115200 0.16% 16‘h0027 76800 0.16% 16‘h0034 57600 0.16% 16‘h004E 38400 0.16% 16‘h009C 19200 0.16% 16‘h00D0 14400 0.16% 16‘h0138 9600...
Page 600: Table 529. Truth Table For Sps, Eps And Pen Bits
LS_Universal asynchronous receiver/transmitter (UART) RM0082 Table 528. UARTLCR_H register bit assignments (continued) Name Reset value Description Word length. This 2 bit field indicates the number of data bits transmitted or received in a frame, according to encoding: – 2‘b00 = 5 [06:05] WLEN 2’h0...
Page 601: Table 530. Uartcr Register Bit Assignments
RM0082 LS_Universal asynchronous receiver/transmitter (UART) Table 529. Truth table for SPS, EPS and PEN bits (continued) Parity bit 1‘b1 1‘b0 1‘b1 1‘b1 1‘b1 1‘b1 Note: Baud rate and line control registers (UARTIBRD, UARTFBRD and UARTLCR_H) must not be changed: - when UART is enabled, - when completing a transmission or a reception when it has programmed to become disabled.
Page 602: Table 531. Uartifls Register Bit Assignments
LS_Universal asynchronous receiver/transmitter (UART) RM0082 Table 530. UARTCR register bit assignments (continued) Name Reset value Description Transmit enable. Setting this bit the transmit section of UART is enabled. Data [08] 1’h1 transmission occurs for UART signals. When the UART is disabled in the middle of transmission, it completes the current character before stopping.
Page 603: Table 532. Uartimsc Register Bit Assignments
RM0082 LS_Universal asynchronous receiver/transmitter (UART) Table 531. UARTIFLS register bit assignments (continued) Name Reset value Description Receive interrupt FIFO level select. This 3 bit field allows to set the trigger points for the receive interrupt, according to encoding: – 3‘b000 = 1/8 full –...
Page 604: Table 533. Uartris Register Bit Assignments
LS_Universal asynchronous receiver/transmitter (UART) RM0082 Table 532. UARTIMSC register bit assignments (continued) Name Reset value Description [01] CTSMIM 1’h0 nUARTCTS modem interrupt mask (see Section 27.5). [00] RIMIM 1’h0 nUARTRI modem interrupt mask (see Section 27.5). 27.4.10 UARTRIS register The UARTRIS (raw interrupt status) is a 16 bit RO register which gives the current raw status value (prior to masking by UARTIMSC) of the corresponding interrupt.
Page 605: Table 535. Uarticr Register Bit Assignments
RM0082 LS_Universal asynchronous receiver/transmitter (UART) Table 534. UARTMIS register bit assignments (continued) Name Reset value Description [09] BEMIS 1’h0 Break error masked interrupt status. [08] PEMIS 1’h0 Parity error masked interrupt status. [07] FEMIS 1’h0 Framing error masked interrupt status. [06] RTMIS 1’h0...
Page 606: Table 536. Uartdmacr Register Bit Assignments
LS_Universal asynchronous receiver/transmitter (UART) RM0082 27.4.13 UARTDMACR register The UARTDMACR (DMA control) is the 16 bit RW DMA control register. The UARTDMACR bit assignments are given in Table 536. Table 536. UARTDMACR register bit assignments Name Reset value Description [15:03] Reserved Read: as zero.
Page 607: Overview
LS_I2C controller LS_I2C controller This chapter describes the I2C Controller which is part of the low speed connectivity subsystem of the SPEAr device. SPEAr300 has two I2C interfaces - one in fixed logic and another in the RAS subsystem. 28.1 Overview The I2C Controller provides an APB interface to the processor to access the two-wire serial I2C bus.
Page 608: Figure 61. I 2 C Controller Functional Block Diagram
LS_I2C controller RM0082 Figure 61. I C controller functional block diagram I2C Controller I2C Master/ APB Slave Slave Interface Interrupts TX -FIFO RX Filter RX -FIFO I2C Debug Clock Generator Interface 28.3 Main functions description This chapter describes the functional behavior of I2C in more detail. 28.3.1 APB interface The host processor accesses data, control and status information on the I...
Page 609: Table 538. First Byte Assignment In Addressing Slave Protocol
RM0082 LS_I2C controller Figure 62. START and STOP conditions [from I C-bus specification] STOP Condition START Condition Addressing slave protocol Two address formats are supported: the 7 bit address format and the 10 bit address format. In case of the 7 bit address format, the first seven bits (bits 7 to 1) of the first byte sent on the bus after the START condition set the slave address, while the LSB is the data direction bit.
Page 610: Figure 63. Start Byte Procedure [From I 2 C-Bus Specification]
LS_I2C controller RM0082 Transmitting and receiving protocol All data is transmitted in byte format, with no limits on the number of bytes transferred per data transfer. After the master sends the slave address and the data direction bit, or the master transmits a byte of data to the slave, the slave-receiver must respond with the acknowledge signal after every byte of data is received.
Page 611: Dma Controller Interface
RM0082 LS_I2C controller A hardware receiver does not respond to the START byte because it is a reserved address and it resets after the Sr (restart condition) is generated. 28.3.3 DMA controller interface The I2C Controller has a handshaking interface to request and control transfers from the DMA Controller of the SPEAr device.
Page 612: Operation Modes
LS_I2C controller RM0082 continuously; that is, when the FIFO begins to fill, another DMA transfer is requested. Otherwise, the FIFO will fill with data (overflow). To prevent this condition, the user must correctly set the watermark level." Choosing the receive watermark level Similar to choosing the transmit watermark level described earlier, the receive watermark level should be set to minimize the probability of overflow.
Page 613 RM0082 LS_I2C controller Slave-transmitter operation When another master addresses the I C controller to requests data, the I C controller acts as a “slave-transmitter,” and the following steps occur: ● The other master initiates an I C transfer with an address that matches the slave address in the IC_SAR register (Section 28.6.5) of the slave I...
Page 614: Master Mode
LS_I2C controller RM0082 If the remote master is to receive n bytes from the I C controller but a number of bytes larger than n is written to the Transmit FIFO then, when the slave finishes sending the requested n bytes, it will clear the Transmit FIFO and ignore any excess bytes.
Page 615: Multi-Master Mode
RM0082 LS_I2C controller Note: If a bulk read is performed on the slave part of the DW_apb_i2c over the I C bus, then only MST_ACTIVITY must be IDLE. that is, the Transmit FIFO does not need to be completely empty. This is a very specific case and should be monitored in software. ●...
Page 616: Figure 64. Multiple Master Arbitration
LS_I2C controller RM0082 Figure 64. Multiple master arbitration ‘1’ DATA1 DATA1 loses arbitration matching data DATA2 ‘0’ SDA mirrors DATA2 SDA lines up with DATA1 START condition Clock synchronization All masters generate their own clock to transfer messages, and data is valid only during the high period of SCL clock.
Page 617: Figure 65. Clock Synchronization
RM0082 LS_I2C controller Figure 65. Clock synchronization Wait Start counting HIGH State period CLKA CLKB SCL LOW Transition Resets all CLKs SCL Transitions HIGH to start when all CLKs are in HIGH state counting their LOW periods 28.5 Interrupt sources The following Table 539 lists the interrupt generated within the I...
Page 618: Table 539. I 2 C Controller Interrupt Sources
LS_I2C controller RM0082 Table 539. I C controller interrupt sources (continued) Name Source Indicates transmission abort. This bit is set to ‘b1 when the I C controller, acting as a master, is unable to complete a command that the processor has sent. Several conditions could cause this interrupt to be issued: –...
Page 619: Table 540. External Pin Connections
RM0082 LS_I2C controller Table 539. I C controller interrupt sources (continued) Name Source Receive buffer filled to IC_RX_BUFFER_DEPTH. RX_OVER This bit is set when the receive buffer was completely filled to IC_RX_BUFFER_DEPTH and more data arrived. The data is lost. Receive buffer empty.
Page 620: Table 541. I2C Registers
LS_I2C controller RM0082 Table 541. I2C registers (continued) Width Name Offset (bit) Type Reset value Description IC_SS_SCL_LCNT Standard-Speed I2C 0x018 16'h0310 (Section 28.6.9) Clock SCL Low Count. IC_FS_SCL_HCNT Fast-Speed I2C Clock 0x01C 16 16'h0064 SCL High Count. (Section 28.6.10) IC_FS_SCL_LCNT Fast-Speed I2C Clock 0x020 16'h00d9...
Page 621: Ic_Con Register(0X000)
RM0082 LS_I2C controller Table 541. I2C registers (continued) Width Name Offset (bit) Type Reset value Description IC_STATUS(Section 28.6.22) 0x070 7'h06 I2C Status IC_TXFLR (Section 28.6.23) 0x074 4’h0 Transmit FIFO Level. IC_RXFLR (Section 28.6.23) 0x078 4’h0 Receive FIFO Level. 0x07C - Reserved IC_TX_ABRT_SOURCE I2C Transmit Abort...
Page 622: Table 542. Ic_Con Register Bit Assignments
LS_I2C controller RM0082 Table 542. IC_CON register bit assignments Reset Name Type Description value [15:07] Reserved Read: undefined. Write: should be zero. Slave disabled after reset. This bit controls whether the I C controller has its slave disabled after reset, according to the [06] IC_SLAVE_DISABLE 1’h0...
Page 623: Ic_Tar Register(0X004)
RM0082 LS_I2C controller Table 542. IC_CON register bit assignments (continued) Reset Name Type Description value Controls operation speed. This 2 bit field controls at which speed the I controller operates, according to the encoding: ‘b00, Illegal = - ‘b01, Standard = 100 kbit/s ‘b10, Fast = 400 kbit/s ‘b11, High = 3.4 Mbit/s (default) If the device is configured for fast or standard...
Page 624: Table 543. Ic_Tar Register Bit Assignments
LS_I2C controller RM0082 Table 543. IC_TAR register bit assignments Reset Name Type Description value [15:13] Reserved Read: undefined. Write: should be zero. 10 bit addressing mode (when acting as master). this bit controls whether DW_apb_i2c starts its IC_10BITADDR_MAST transfer in 10 bit addressing mode when acting [12] 1’h0 as a master according to the encoding below:...
Page 625: Table 544. Ic_Sar Register Bit Assignments
RM0082 LS_I2C controller Table 544. IC_SAR register bit assignments Reset Name Type Description value [15:10] Reserved Read: undefined. Write: should be zero. [09:00] IC_SAR 10’h55 Slave address. 28.6.6 IC_HS_MADDR register(0x00C) The IC_HS_MADDR is the RW register which holds the 3 bit value of the I C master code in HS (high-speed) mode.
Page 626: Table 547. Ic_Ss_Scl_Hcnt Register Bit Assignments
LS_I2C controller RM0082 Table 546. IC_DATA_CMD register bit assignments (continued) Reset Name Type Description value Control read or write. This bit controls whether a read or write is performed, according to the encoding: 1‘b0 = Write. 1‘b1 = Read. Note: In case of reading, the lower bits from 7 to 0 (DAT field) are ignored by the [08] 1‘h0...
Page 627: Table 548. Ic_Ss_Scl_Hcnt Sample Calculations
RM0082 LS_I2C controller Table 548. IC_SS_SCL_HCNT sample calculations SCL clock SCL high time SCL high time C data rate - SS IC_SS_SCL_HCNT frequency required min actual (Kbps) (hex/decimal) (MHz) (µs) (µs) 16‘h0008/’d8 4.00 16‘h001B/’d27 4.09 16‘h0028/’d40 4.00 16‘h012C/’d300 4.00 16‘h0190/’d400 4.00 16‘h01F4/’d500 4.00...
Page 628: Table 551. Ic_Fs_Scl_Hcnt Register Bit Assignments
LS_I2C controller RM0082 Table 550. IC_SS_SCL_LCNT sample calculations (continued) SCL clock SCL low time SCL low C data rate - SS IC_SS_SCL_LCNT frequency required min timeactual (Kbps) (hex/decimal) (MHz) (µs) (µs) 16‘h024C/’d588 4.70 1000 16‘h125C/’d4700 4.70 28.6.10 IC_FS_SCL_HCNT register(0x01C) The IC_FS_SCL_HCNT is a 16 bit RW register which allows to set the high period of the SCL clock for fast-speed mode.
Page 629: Table 553. Ic_Fs_Scl_Lcnt Register Bit Assignments
RM0082 LS_I2C controller 28.6.11 IC_FS_SCL_LCNT register(0x020) The IC_FS_SCL_LCNT is a 16 bit RW register which allows to set the low period of the SCL clock for fast-speed mode. The IC_FS_SCL_LCNT bit assignments are given in Table 553. Note: This register can be written only when the I C controller is disabled, which corresponds to the IC_ENABLE (Section...
Page 630: Table 555. Ic_Hs_Scl_Hcnt Register Bit Assignments
LS_I2C controller RM0082 Note: This register can be written only when the I C controller is disabled, which corresponds to the IC_ENABLE (Section 28.6.21) register being set to ‘b0. Write at other times has no effect. This register must be set before any I C bus transaction can take place in order to ensure proper I/O timing.
Page 631: Table 557. Ic_Hs_Scl_Lcnt Register Bit Assignments
RM0082 LS_I2C controller Table 557. IC_HS_SCL_LCNT register bit assignments Reset Name Description value SCL clock low period count for high speed. This 16 bit field states the SCL clock low period 16'h00 count for high speed. The minimum valid value is [15:00] IC_HS_SCL_LCNT 8, and hardware prevents that a value less than...
Page 632: Table 560. Ic_Intr_Mask Register Bit Assignments
LS_I2C controller RM0082 Table 559. IC_INTR_STAT register bit assignments (continued) Reset Name Type Description value [11] R_GEN_CALL 1’h0 [10] R_START_DET 1’h0 [09] R_STOP_DET 1’h0 [08] R_ACTIVITY 1’h0 [07] R_RX_DONE 1’h0 [06] R_TX_ABRT 1’h0 Refer to Section 28.5 for a detailed description of these interrupt sources.
Page 633: Table 561. Ic_Raw_Intr_Stat Register Bit Assignments
RM0082 LS_I2C controller Note: M_GEN_CALL bit should be set to 1 when IC_ACK_GENERAL_CALL register is set to 0. 28.6.16 IC_RAW_INTR_STAT register(0x034) The IC_RAW_INTR_STAT is a RO register which indicates the raw interrupt status (prior to masking by IC_INTR_MASK register, Section 28.6.15) of the I C controller.
Page 634: Table 562. Ic_Rx_Tl Register Bit Assignments
LS_I2C controller RM0082 Table 562. IC_RX_TL register bit assignments Reset Name Type Description value [15:08] Reserved Read: undefined. Write: should be zero. RX_FULL interrupt threshold. This 8 bit field value is the number of entries in the receive FIFO of the I C controller which defines the RX_FULL interrupt threshold, as (RX_TL + 1).
Page 635: Table 564. Ic_Clr_Intr Register Bit Assignments
RM0082 LS_I2C controller Table 564. IC_CLR_INTR register bit assignments Reset Name Type Description value [15:01] Reserved Read: undefined. Reading this register causes interrupt to be [00] CLR_INTR 1’h0 cleared. 28.6.20 Interrupt clearing registers(0x044 - 0x068) With the aim to clear an individual interrupt (among those supported by the I C controller, and listed in Section...
Page 636: Table 566. Ic_Enable Register Bit Assignments
LS_I2C controller RM0082 Table 566. IC_ENABLE register bit assignments Reset Name Type Description value [15:01] Reserved Read: undefined. Write: should be zero. C controller enable. Setting this bit, the I C controller is enabled, otherwise (bit cleared) it is disabled. Software should not disable the I C controller while it is active.
Page 637: Table 568. Ic_Txflr And Ic_Rxflr Register Bit Assignments
RM0082 LS_I2C controller Table 567. IC_STATUS register bit assignments (continued) Reset Name Description value Receive FIFO not empty. If set, this bit indicates that the receive FIFO contains one or more entries. This bit is cleared [03] RFNE 1’h0 when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO.
Page 638: Table 569. Ic_Tx_Abrt_Source Register Bit Assignments
LS_I2C controller RM0082 Table 569. IC_TX_ABRT_SOURCE register bit assignments Reset Name Type Description value [31:16] Reserved Read: undefined. Write: should be zero. Slave requesting data to transmit. If set, this bit indicates that the slave is [15] ABRT_SLVRD_INTX 1’h0 requesting data to transmit and the user wrote a read command into the transmit FIFO.
Page 639: Ic_Dma_Cr Register (0X088)
RM0082 LS_I2C controller Table 569. IC_TX_ABRT_SOURCE register bit assignments (continued) Reset Name Type Description value Master in high speed mode. If set, this bit indicates that the master is in [06] ABRT_HS_ACKDET 1’h0 high-speed mode and the high-speed master code was acknowledge (wrong behavior). Master sent a general call.
Page 640: Table 570. Ic_Dma_Cr Register Bit Assignments
LS_I2C controller RM0082 Table 570. IC_DMA_CR register bit assignments Name Reset value Description [15:02] Reserved Read. undefined write: should be zero. Transmit DMA enable. [01] TDMAE 1’h0 Setting this bit, it enables the transmit FIFO DMA channel. Otherwise (bit cleared) it is disabled. Receive DMA enable.
Page 641: Table 573. Ic_Comp_Param Register Bit Assignments
RM0082 LS_I2C controller 28.6.28 IC_COMP_PARAM1 register (0x0F4) The IC_COMP_PARAM1 (component parameter register 1) is a RO register which contains encoded information about the component’s parameter setting. The IC_COMP_PARAM1 bit assignments are given in Table 573. Table 573. IC_COMP_PARAM register bit assignments Reset Name Type...
Page 642 LS_I2C controller RM0082 Table 573. IC_COMP_PARAM register bit assignments (continued) Reset Name Type Description value Maximum speed mode. This 2 bit field indicates the maximum supported operation mode for the I controller, according to the encoding: [03:02] MAX_SPEED_MODE 2’h3 – 2‘b00 = Reserved. –...
Page 643: Figure 66. Adc Block Diagram
RM0082 LS_Analog to digital convertor (ADC) LS_Analog to digital convertor (ADC) 29.1 Overview Within its Low Speed Subsystem, the device includes an Analog-to-Digital Converter (ADC), which is connected to the APB bus. Main features of the ADC are listed below: ●...
Page 644: Operating Sequence
LS_Analog to digital convertor (ADC) RM0082 29.3 Operating sequence 29.3.1 Normal mode As long as POWER DOWN bit in ADC_STATUS_REG register (Section 29.5.1) is set to logic’0’, the ADC is inactive (disabled) and output latches contain last conversion. Setting the POWER DOWN bit, the ADC enters in its functional mode after 50 us, when a conversion can be then initiated setting the ENABLE bit in ADC_STATUS_REG register (Section 29.5.1).
Page 645: Table 574. External Pin Connection
RM0082 LS_Analog to digital convertor (ADC) 29.4 Programming model 29.4.1 External pin connection Table 574. External pin connection Signal Ball VREF+ VREF- AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 The ADC can be fully configured by programming a set of 16 bit wide registers (listed in Table 575) which can be accessed at the base address 0xD008_0000.
Page 646: Register Description
LS_Analog to digital convertor (ADC) RM0082 Table 575. ADC registers summary (continued) SIZE Reset Register name Offset Type Description value [bit] Channel 6 control register CH6_CTRL 0x0028 4’h0 (enhanced mode) Channel 7 control register CH7_CTRL 0x002C 4 4’h0 (enhanced mode) Channel 0 Data register CH0_DATA 0x0030...
Page 647: Table 576. Adc_Status_Reg Register
RM0082 LS_Analog to digital convertor (ADC) Table 576. ADC_STATUS_REG register (continued) Reset Name value Type Description DMA Request Enable (For Channel 0 only) – 1’b0 - No DMA request [12] DMA ENABLE 1’h0 – 1’b1 - DMA Request generated when the channel 0 conversion is done.
Page 648: Table 577. Conversion Data Bits Position In Average_Reg (High Resolution = 0)
LS_Analog to digital convertor (ADC) RM0082 Table 576. ADC_STATUS_REG register (continued) Reset Name value Type Description Channel selection. This 3 bit field allows to select one of the 8 analog input (AIN) channels, according to encoding: – 3‘b000 = AIN[0] –...
Page 649: Table 579. Scan Rate Register Bit Assignments
RM0082 LS_Analog to digital convertor (ADC) Table 578. Conversion data bits position in AVERAGE_REG (High Resolution = 1) Integer part of the Fractional part of the ADC_STATUS_REG[7:5] Number of samples result result 3‘b100 bits [13:4] bits [3:0] 3’b101 bits [14:5] bits [4:0] 3‘b110 bits [15:6]...
Page 650: Table 581. Chx Ctrl Register Bit Assignments
LS_Analog to digital convertor (ADC) RM0082 Because the frequency of ADC clock ranges from 3 MHz to 14 MHz, it follows that: ⎛ ⎞ ⎛ ⎞ PB CLK Freq APB CLK Freq ------------------------------------- - ------------------------------------------ - ≤ ≤ ADC CLK H ADC CLK L ⎝...
Page 651: Table 582. Chx Data Register (Normal Mode) Bit Assignments
RM0082 LS_Analog to digital convertor (ADC) Table 582. CHx DATA register (normal mode) bit assignments Reset Name Type Description value VALID DATA bit: [17] VALID DATA- 1‘h0 1’b0 - CONVERSION DATA field not valid 1’b1 - CONVERSION DATA field valid [16:10] RESERVED reserved [09:00] CONVERSION DATA...
Page 652: Rs_Reconfigurable Array Subsystem (Ras) Registers
PLGPIO[54:49],PLGPIO[80:59] are configured as output and drive logic '0' on these pads. 30.1.1 NAND mode This mode is the default mode for SPEAr300. This mode supports the FSMC interface for NAND Flash connectivity along with some boot pins which gives information to the Boot 652/844...
Page 653: Nor Mode
RM0082 RS_Reconfigurable array subsystem (RAS) registers ROM about the way booting is to be done. The following sub-section explains the features supported by each IP present in this mode; FSMC interface for NAND Flash connectivity (16 bits, 5 control signals) Boot pins 30.1.2 NOR mode...
Page 654: Hend_Ip_Phone Mode (High End Ip Phone)
RS_Reconfigurable array subsystem (RAS) registers RM0082 30.1.5 HEND_IP_PHONE MODE (HIGH END IP PHONE) In this mode, following IPs are present; 9 x 9 Keyboard LCD Controller Interface 4 SPI/I2C Control signals Digital-to-Analog converter (DAC) I2S Block TDM block capable of communicating with 2 external devices SD/SDIO/MMC host controller Fully configurable Telecom GPIO8(7-4) and GPIO10(9-0) 30.1.6...
Page 655: Ata_Pabx_I2S Mode (Ata Pabx With I2S)
RM0082 RS_Reconfigurable array subsystem (RAS) registers 30.1.9 ATA_PABX_I2S MODE (ATA PABX with I2S) In this mode, following IPs are present; FSMC with 8 bit NOR/NAND Flash interface 7 Interrupt pins 8 SPI/I2C Control signals Digital-to-Analog converter I2S Block TDM block capable of communicating with 4 external devices SD/SDIO/MMC host controller supporting max.
Page 656: Camu_Wlcd Mode (14 Bit Camera Without Lcd)
RS_Reconfigurable array subsystem (RAS) registers RM0082 30.1.12 CAMu_wLCD MODE (14 bit CAMERA without LCD) In this mode, following IPs are present; 14 Bit Camera interface 7 x 5 Keyboard Digital-to-Analog converter I2S Block TDM block capable of communicating with 2 external devices SD/SDIO/MMC host controller Fully configurable Telecom GPIO8(5-4) and GPIO10(9-4) 30.1.13...
Page 657: Table 584. Ras Address Space
RM0082 RS_Reconfigurable array subsystem (RAS) registers Table 584. RAS address space Base Address Address Space 0x5000_0000 0x5000_0000 - 0x5FFF_FFFF TELECOM 0x6000_0000 0x6000_0000 - 0x6FFF_FFFF CLCD 0x7000_0000 0x7000_0000 - 0x7FFF_FFFF SDIO 0x8000_0000 0x8000_0000 - 0x98FF_FFFF FSMC 0x9900_0000 0x9900_0000 - 0x9FFF_FFFF RAS Registers 0xA000_0000 0xA000_0000-0xAFFF_FFFF APB Blocks...
Page 658: Table 588. Ras Register 1 Description
RS_Reconfigurable array subsystem (RAS) registers RM0082 Table 587. RAS memory map Start address End address Peripheral Notes 0x5001_0000 0x5001_0FFF Action memory 0x5003_0000 0x5003_7FFF Buffer memory 0x5004_0000 0x5004_0FFF Sync memory 0x5005_0000 0x5005_0FFF memory bank 1 0x5005_1000 0x5005_1FFF memory bank 2 0x6000_0000 0x6FFF_FFFF CLCD 0x7000_0000...
Page 659: Table 589. Ras Register 2 Description
RM0082 RS_Reconfigurable array subsystem (RAS) registers Table 588. RAS Register 1 description Default Field Description Value [12] 1’h0 SSP enhanced (CS(2-3-4)) [11] 1’h0 SSP Basic (no CS(2-3-4)) [10] 1’h0 MAC Ethernet [09] 1’h0 basGPIO (0) [08] 1’h0 basGPIO(1) [07] 1’h0 basGPIO(2) [06] 1’h0...
Page 660: Table 590. Ras Interrupt Assignment
RS_Reconfigurable array subsystem (RAS) registers RM0082 Table 589. RAS Register 2 description (continued) Default Field Description Value These bits are used for dynamic selection of NAND or NOR on each bank of FSMC. Each bit corresponds to a bank of FSMC. For e.g. Bit24 corresponds to Bank0 Bit25 corresponds to Bank1 and so on…...
Page 661: Table 591. Ras Dma Configuration
RM0082 RS_Reconfigurable array subsystem (RAS) registers 30.6 RAS DMA configuration Table 591. RAS DMA configuration Request RAS IP RAS_DMA_REQ[0] Not Used RAS_DMA_REQ[1] RAS_DMA_REQ[2] RAS_DMA_REQ[3] CAMERA RAS_DMA_REQ[4] Not Used RAS_DMA_REQ[5] Not Used RAS_DMA_REQ[6] Not Used RAS_DMA_REQ[7] Not Used RAS_DMA_REQ[8] Not Used RAS_DMA_REQ[9] Not Used RAS_DMA_REQ[10]...
Page 662: Overview
RS_Flexible static memory controller (FSMC) 31.1 Overview Within its Reconfigurable Array Subsystem, SPEAr300 provides a Flexible Static Memory Controller (FSMC) which is intended to interface an AHB bus to external NAND/NOR Flash memories and to asynchronous SRAM memories. The controller: ●...
Page 663: Figure 67. Fsmc Block Diagram
RM0082 RS_Flexible static memory controller (FSMC) 31.2 Functional description 31.2.1 Block diagram Figure 67. FSMC block diagram Configuration Register NAND/NOR Flash Driver Interface 31.3 Description 31.3.1 AHB interface The AHB Interface block provides the FSMC interface to the AHB bus. It decomposes the system bus transfers into external accesses supported by the selected external device.
Page 664: Table 592. Parallel Nor Flash
NOR Flash have address valid signal (ADV) Note: Byte Lane and address valid signal have not been made available on SPEAr300 ports. So SRAMs which require BL inputs cannot be connected. Also, NOR Flash memories requiring ADV input cannot be connected.
Page 665: Table 593. Nand Flash
RM0082 RS_Flexible static memory controller (FSMC) Table 593. NAND Flash Signal Direction Description D[15:0] Bidir Data lines. Command Latch Enable Active High. Address Latch Enable Active High. Write Enable Active Low. Read Enable Active Low. /E1, /E2, /E3 and /E4 Chip Enable Active Low.
Page 666: Table 595. Fsmc Control And Timing Registers Summary
RS_Flexible static memory controller (FSMC) RM0082 The FSMC registers are usually initialized at boot time, however it is possible to change them at any moment. FSMC registers can be logically arranged in two main groups: ● Control and timing registers (listed inTable 595): for FSMC configuration ●...
Page 667: Table 596. Fsmc Identification Registers Summary
RM0082 RS_Flexible static memory controller (FSMC) Table 595. FSMC control and timing registers summary (continued) Name Offset Type Description Timings of NAND 2 in common memory GenMemCtrl_Comm2 0x088 mode. GenMemCtrl_Attrib2 0x08C Timings of NAND 2in attribute memory mode. 0x090 to Reserved.
Page 668 Flash memory, according to the encoding below: [07] Wprot 1'h1 0 - Disabled. 1 - Enabled (default). SPEAr300 Note: Wprot port is not available in Reset/power down signal to Flash memory. This field is applicable only to Flash memories. It directly represents the RstPwdwn RstPwr- [06] 1'h1 signal to the input pin of the Flash memory.
Page 669: Table 598. Genmemctrl_Tim(I) Register Bit Assignments
[01] Muxed 1'h1 0 - Not muxed. SPEAr300 1 - Muxed (Not used in Enable bank. This bit allows to enable/disable the relevant bank, according to the encoding below: 0 - Disabled. 1 - Enabled.
Page 670: Table 599. Genmemctrl_Pc(I) Register Bit Assignments
1 - Enabled Data width. This 2-bit field indicates the data width, according to the encoding below: – 00 - 8 – 01 - 16 SPEAr300 – 10 - 32 (Not used in – 11 - Not used. [05:04] DevWidth This field is valid only if Dev_type (see ‘bit 3’...
Page 671: Table 600. Genmemctrl_Comm(I)/Genmemctrl_Attrib(I) Register Bit Assignments
RM0082 RS_Flexible static memory controller (FSMC) 31.4.8 GenMemCtrl_Comm(i)/GenMemCtrl_Attrib(i) registers Each GenMemCtrl_Comm(i)/GenMemCtrl_Attrib(i) (with i = 0...3) is a RW register which contain the timing control information of each bank used for NAND Flash memories. The GenMemCtrl_Comm(i)/GenMemCtrl_Attrib(i) bit assignments are given in Table 600.
Page 672: Table 602. Genmemctrlperiphid0 Register Bit Assignments
RS_Flexible static memory controller (FSMC) RM0082 31.4.10 GenMemCtrl peripheral identification registers (GenMemCtrlPeripID0- The GenMemCtrlPeriphID0-3 registers are four read only 8-bit registers. The bit assignments are:- Table 602. GenMemCtrlPeriphID0 register bit assignments Reset Name Description value [31:08] Reserved. Read undefined. Write: should be zero. [07:00] PartNumber0 8'h90...
Page 673: Table 606. Genmemctrlperiphid3 Register Bit Assignments
RM0082 RS_Flexible static memory controller (FSMC) Table 606. GenMemCtrlPeriphID3 register bit assignments Reset Name Description value [31:08] Reserved. Read undefined. Write: should be zero. GenMemC [07:00] 8'h0D These bits read back as 0x0D trlPCellID0 Table 607. GenMemCtrlPeriphID1 register bit assignments Reset Name Description...
Page 674 RS_Flexible static memory controller (FSMC) RM0082 The delays are: tset = (Tset_value + 1) * clock period twait = (Twait_value + 1) * clock period thold = (Thold_value) * clock period thiz = (Thiz_value) * clock period So timing registers must be programmed with this value: Tset =(timing for tset/clock period) -1 Twait =(timing for twait/clock period) -1 Thiz=(timing for thiz/clock period)
Page 675 RM0082 RS_Flexible static memory controller (FSMC) Tset computation Choose the biggest among: tcs, tcls - TCS*TCLK tar - TCS*TCLK tals tclr twh -TCS*TCLK treh - (TCS+Thold)*TCLK tir + tdh -(TCS+Thold)*TCLK ======> tset Tset = int((tset + Dtoutdel)/TCLK) Twait computation Chose the biggest among: twp, trp.
Page 676 RS_Flexible static memory controller (FSMC) RM0082 Thold computation No wait signal expected (common memory): Chose the biggest among: talh, tch, twc - (Tset + 1 + Twait + 1) * TCLK trc - (Tset + 1 + Twait + 1) * TCLK twhr - (Tset+1+TCS) * TCLK tclh ======>...
Page 677 RM0082 RS_Flexible static memory controller (FSMC) NOR Flash Interface taddr_st=max between: tavlh, twhwl. =====> taddr_st Taddr_st = int((taddr_st+Dtoutdel)/TCLK) Thold_add = int((tlhax+Dtoutdel)/TCLK) Tdata_st = int((tllqv + tdelout + tdelin)/TCLK) - Taddr_st -1 tBusTurn is the max between: tehqz tghqz. TBusTurn=int((tBusTurn + tindel + toutdel)/TCLK) The minimum value for TBusTurn is 3.
Page 678: Overview
RS_SDIO controller 32.1 Overview Within the Reconfigurable Array Subsystem, SPEAr300 can provides an SDIO host controller that has an AMBA compatible interface and conforms to the SD host Controller Standard Specification Version 2.0. It handles SDIO/SD Protocol at transmission level, packing data, adding cyclic redundancy check (CRC), start/end bit and checking for transaction format correctness.
Page 679: Table 610. Signal Interface
RM0082 RS_SDIO controller 32.3 Signal interface Figure 68. SDIO controller pin diagram SD_CLK AHB SLAVE DATA[7:0] AHB MASTER SDIO_CMD SDIO Controller SDIO_WP CLK48MHz SDIO_CD INTERRUPT TO ARM LED_ON Table 610. Signal interface Group Signal name Direction Size Description HCLK AHB system clock GLOBAL HRESETn AHB system reset...
Page 680: Table 611. Ahb Master/Target Interface
RS_SDIO controller RM0082 32.4 Pin signals The Arasan SD2.0/SDIO2.0 Host Controller has six main interface groups: ● ARM processor Interface signals. ● SD2.0/SDIO2.0/MMC4.2 Card Interface that forms the main card interface. ● System interface providing the clock and reset signals. ●...
Page 681 RM0082 RS_SDIO controller Table 612. SD2.0/SDIO2.0/MMC4.2 card interface (continued) Signal Description SD1/SD4/SD8 mode: Command output CMD_OUT SPI : Command output and write data SD1/SD4/SD8 mode : Command output enable CMD_OUT_EN SPI mode: Command output enable and write data enable SD1/SD4/SD8 mode : Data0 input DATA0_IN SPI mode : Command response input, read data and crc status for write data...
Page 682: Table 613. System Interface
RS_SDIO controller RM0082 Table 612. SD2.0/SDIO2.0/MMC4.2 card interface (continued) Signal Description SDCD_n Active Low. Card Detection for single slot SDWP Active High. SD card write protect LED ON : Tp caution the user not to remove the card while the led_on SD card is being accessed Table 613.
Page 683: Figure 69. Architectural Block Diagram
RM0082 RS_SDIO controller Table 614. RAM Interface signals (continued) Signal Description DB_RAM2[31:0] Data in for PORT B FIFO 2 CENB_RAM2 Chip enable for PORT B FIFO 2 WENB_RAM2 Write enable for PORT B FIFO 2 QA_RAM1[31:0] DATA OUT From PORT A FIFO 1 QB_RAM1[31:0] DATA OUT From PORT B FIFO 1 QA_RAM2[31:0]...
Page 684: Figure 70. Sd Card Detection
RS_SDIO controller RM0082 32.5.1 Sequence This section defines some basic sequence flows of initialization and data transfer with the card. Figure 70. SD card detection Start Enable Int of Card Detect Card Detect Int occur Clr Card Detect Int Status Card Inserted is 0b, then recognize as removal Check...
Page 685: Figure 71. Sd Clock Supply Sequence
RM0082 RS_SDIO controller Figure 71. SD clock supply sequence Start Calculate a divisor for SD clock frequency Set SDCLK Frequency Select and Internal Clock Enable Internal Clock Stable = 0b Check Internal Clock Stable Internal Clock Stable = 1b Set SD Clock On Supply SD Clock Calculate a divisor to determine SD Clock frequency.
Page 686: Figure 72. Command Issue Sequence
RS_SDIO controller RM0082 Figure 72. Command issue sequence Start CMD Line used Check Command Inhibit (CMD) CMD Line free Issue the command with the busy? Issue Abort Command? DAT Lone used Check Command Inhibit(DAT) DAT Lone free New command can be issued Set Argument Reg Set Command Reg Command Complete Sequence...
Page 687: Figure 73. Command Completion Sequence
RM0082 RS_SDIO controller Figure 73. Command completion sequence Start Wait for Command Complete Int Command Complete Int occur Clr Command Complete Status Get Response Data Command with Transfer Complete Int? Wait for Transfer Complete Int Transfer Complete Int occur Clr Transfer Complete Status Error Check Response Data...
Page 688 RS_SDIO controller RM0082 Wait for the Command Complete Interrupt. If the Command Complete Interrupt has occurred, go to step (2). Write logic ‘1’ to Command Complete in the Normal Interrupt Status register to clear this bit. Read the Response register and get necessary information of the issued command. Judge whether the command uses the Transfer Complete Interrupt or not.
Page 689: Figure 74. Data Transaction Sequence Without Dma
RM0082 RS_SDIO controller Figure 74. Data transaction sequence without DMA Start Set Command Reg Set Block Size Reg Wait for Set Block Count Reg Command Complete Int Command Complete Int occur Set Argument Reg Clr Command Complete Status Set Transfer Mode Reg Get Response Data Read Write...
Page 690 RS_SDIO controller RM0082 Set the value to Block Size register. Set the value to Block Count register. Set the argument value to Argument register. Set the value to the Transfer Mode register. The host driver determines Multi / Single Block Select, Block Count Enable, Data Transfer Direction, Auto CMD12 Enable and DMA Enable.
Page 691: Figure 75. Data Transaction Sequence With Sdma
RM0082 RS_SDIO controller Figure 75. Data transaction sequence with SDMA Start Set System Address Reg (10) Wait for Set Block Size Reg Transfer Complete Int and DMA Int Transfer (11) Complete Int Set Block Count Reg occur Check Interrupt Status DMA Int occur (12) Set Argument Reg...
Page 692 RS_SDIO controller RM0082 Data location of system memory is set to the SDMA System Address register. Set the value to the Block Size register. Set the value to the Block Count register. Set the argument value to the Argument register. Set the value to the Transfer Mode register.
Page 693: Figure 76. Data Transaction Sequence With Adma
RM0082 RS_SDIO controller Figure 76. Data transaction sequence with ADMA Start Create Discriptor table (11) Wait for Set ADMA System Address Reg Transfer Complete Int and ADMA Error Int (12) ADMA Error Int occurs Set Block Size Reg Check Interrupt Status Transfer Complete Int occurs (13)
Page 694: Figure 77. Abort Transaction Sequence
RS_SDIO controller RM0082 read operation is aborted asynchronously and extra read data is discarded when the ADMA is completed. Set the argument value to the Argument register. Set the value to the Transfer Mode register. The host driver determines Multi / Single Block Select, Block Count Enable, Data Transfer Direction, Auto CMD12 Enable and DMA Enable.
Page 695: Table 615. Sdio Registers Map
RM0082 RS_SDIO controller synchronous abort, the host controller shall issue an Abort Command after the data transfer stopped by using Stop At Block Gap Request in the Block Gap Control register. 32.6 Programmer's model This section describes the programmer’s model. 32.6.1 Register map The SDIO Controller can be configured by programming registers through the AHB slave...
Page 696: Table 616. Register Field Types
RS_SDIO controller RM0082 Table 615. SDIO registers map (continued) Name Offset Size in bit Description 0x03E Reserved CAP1 0x040 Capabilities registers CAP2 0x044 Reserved MAXCURR1 0x048 Maximum current capabilities register MAXCURR2 0x04C Reserved Force event register for auto CMD12 ACMD12FEERSTS 0x050 error status Force event register for error interrupt...
Page 697: Table 617. Sdmasysaddr Register Bit Assignments
RM0082 RS_SDIO controller 32.7 Register description This section describes the register of SDIO. 32.7.1 SDMASysAddr register This register contains the system memory address for a DMA transfer. When the Host Controller (HC) stops a DMA transfer, this register shall point to the system address of the next contiguous data position.
Page 698: Blkcount Register
RS_SDIO controller RM0082 Table 618. BLKSize register bit assignments (continued) Reset Name Type Description value To perform long DMA transfer, System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary specified by these fields and the HC generates the DMA Interrupt to request the HD to update the System...
Page 699: Table 619. Blkcount Register Bit Assignments
RM0082 RS_SDIO controller Table 619. BLKCount register bit assignments Reset Name Type Description value This register is enabled when Block Count Enable in the Transfer Mode register is set to logic ‘1’ and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero.
Page 700: Table 622. Determination Of Transfer Type
RS_SDIO controller RM0082 Table 621. TRMODE register bit assignments (continued) Reset Name Type Description value This bit enables multiple block DAT line data transfers. 1’b0 - Single Block [05] MSBLKSel 1’h0 1’b1 - Multiple Block See also Table 622. This bit defines the direction of DAT line data transfers.
Page 701: Table 623. Cmd Register Bit Assignments
RM0082 RS_SDIO controller 32.7.6 CMD register The CMD bit assignments are given in Table 623 Table 623. CMD register bit assignments Reset Name Type Description value [15:14] Rsvd Reserved This bit shall be set to the command number [13:08] CMDIndex 6’h0 (CMD0-63, ACMD0- 63).
Page 702: Table 624. Relation Between Parameters And The Name Of Response Type
RS_SDIO controller RM0082 Table 623. CMD register bit assignments (continued) Reset Name Type Description value If this bit is set to 1, the HC shall check the index field in the response to see if it has the same value as the command index.
Page 703: Table 626. Response Bit Definition For Each Response Type
RM0082 RS_SDIO controller Table 626. Response bit definition for each response type Kind of response Meaning of response Response field Response register R1, R1b (normal response) Card Status R[39:8] RESP[31:0] Card Status for Auto R1b (Auto CMD12 response) R[39:8] RESP[127:96] CMD12 R2 (CID, CSD Register) CID or CSD reg.
Page 704 RS_SDIO controller RM0082 Table 628. PRSTATE register bit assignments (continued) Reset Name Type Description value This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. D23 - DAT[3] [23:20] DAT[3:0]LSL...
Page 705 RM0082 RS_SDIO controller Table 628. PRSTATE register bit assignments (continued) Reset Name Type Description value This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is logic ‘1’, data can be written to the buffer.
Page 706 RS_SDIO controller RM0082 Table 628. PRSTATE register bit assignments (continued) Reset Name Type Description value [07:03] Rsvd Reserved This bit indicates whether one of the DAT line on SD bus is in use. 1’b1 - DAT line active 1’b0 - DAT line inactive In the case of read transactions this status indicates if a read transfer is executing on the SD bus.
Page 707: Table 629. Hostctrl Register Bit Assignments
RM0082 RS_SDIO controller 32.7.10 HOSTCTRL register The HOSTCTRL bit assignments are given in Table 629. Table 629. HOSTCTRL register bit assignments Reset Name Type Description value This bit selects source for card detection. [07] CDSD 1’h0 1’b1- The card detect test level is selected 1’b0 -SDCD# is selected (for normal use) This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or...
Page 708: Table 630. Pwrctrl Register Bit Assignments
RS_SDIO controller RM0082 32.7.11 PWRCTL register The PWRCTRL bit assignments are given in Table 630. Table 630. PWRCTRL register bit assignments Reset Name Type Description value [07:04] Rsvd Reserved By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits in the capabilities register.
Page 709 RM0082 RS_SDIO controller Table 631. BLKGAPCTRL register bit assignments (continued) Reset Name Type Description value The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation.
Page 710: Table 632. Wkupctrl Register Bit Assignments
RS_SDIO controller RM0082 Table 631. BLKGAPCTRL register bit assignments (continued) Reset Name Type Description value This bit is used to stop executing a transaction at the next block gap for non- DMA,SDMA and ADMA transfers. Until the transfer complete is set to logic ‘1’, indicating a transfer completion the HD shall leave this bit set to logic ‘1’.
Page 711: Clkctrl Register
RM0082 RS_SDIO controller Table 632. WKUPCTRL register bit assignments (continued) Reset Name Type Description value Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this [02] WEECDR 1’h0...
Page 712: Table 633. Clkctrl Register Bit Assignments
RS_SDIO controller RM0082 Table 633. CLKCTRL register bit assignments Reset Name Type Description value This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register.
Page 713: Table 634. Tmoutctrl Register Bit Assignments
RM0082 RS_SDIO controller Table 633. CLKCTRL register bit assignments (continued) Reset Name Type Description value This bit is set to logic ‘1’ when SD clock is stable after writing to Internal Clock Enable in this register to logic ‘1’. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1.
Page 714: Table 635. Swres Register Bit Assignments
RS_SDIO controller RM0082 32.7.16 SWRES register The SWRES bit assignments are given in Table 635. Table 635. SWRES register bit assignments Reset Name Type Description value [07:03] Rsvd Reserved Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register Buffer is cleared and Initialized.
Page 715: Table 636. Nirqstat Register Bit Assignments
RM0082 RS_SDIO controller Note: A reset pulse is generated when writing logic ‘1’ to each bit of this register. After completing the reset, the HC shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are logic ‘0’. 32.7.17 NIRQSTAT register The Normal Interrupt Status Enable affects read of this register, but Normal Interrupt Signal...
Page 716 RS_SDIO controller RM0082 Table 636. NIRQSTAT register bit assignments (continued) Reset Name Type Description value This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the HD writes this bit to logic ‘1’ to clear this status the status of the Card Inserted in the Present State register should be confirmed.
Page 717: Table 637. Relation Between Transfer Complete And Data Time Out Error
RM0082 RS_SDIO controller Table 636. NIRQSTAT register bit assignments (continued) Reset Name Type Description value This bit is set when a read / write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status.
Page 718: Table 638. Relation Between Command Complete And Time Out Error
RS_SDIO controller RM0082 Table 638. Relation between command complete and time out error Command complete Command time out error Meaning of the status Interrupted by Another Factor. Don’t care Response not received within 64 SDCLK cycles. Response Received 32.7.18 ERRIRQSTAT register Status defined in this register can be enabled by the Error Interrupt Status Enable Register, but not by the Error Interrupt Signal Enable Register.
Page 719 RM0082 RS_SDIO controller Table 639. ERRIRQSTAT register bit assignments (continued) Reset Name Type Description value Auto CMD12 Error Occurs when detecting that one of the bits in AutoCMD12 Error Status register has changed from 0 to 1. This bit is set to logic ‘1’ also when Auto [08] ACMD12ERR 1’h0 RW1C...
Page 720: Table 640. Relation Between Command Crc Error End Time Out Error
RS_SDIO controller RM0082 Table 639. ERRIRQSTAT register bit assignments (continued) Reset Name Type Description value Occurs if a Command Index error occurs in the Command Response. [03] CMDIDXERR 1’h0 RW1C 1’b0 - No Error 1’b1 - Error Occurs when detecting that the end bit of a command response is 0.
Page 721: Table 641. Nirqstaten Register Bit Assignments
RM0082 RS_SDIO controller Table 641. NIRQSTATEN register bit assignments Reset Name Type Description value The HC shall control error Interrupts using the Error [15] FIX0 1’h0 Interrupt Status Enable register. [14:09] Rsvd Reserved If this bit is set to logic ‘0’, the HC shall clear Interrupt request to the System.
Page 722: Table 643. Nirqsigen Register Bit Assignments
RS_SDIO controller RM0082 Table 642. ERRIRQSTATEN register bit assignments (continued) Name Reset value Type Description [09] ADMAERSTSEN [08] ACMD12ERSTSEN [07] CURLERSTSEN [06] DATAEBSTSEN [05] DATACRCERSTSEN 1’b0 - Masked 1’b1 - Enabled [04] DATATOERSTSEN [03] CMDIDXERSTSEN [02] CMDEBERSTSEN [01] CMDCRCERSTSEN [00] CMDTOERSTSEN 32.7.21 NIRQSIGEN register...
Page 723: Table 644. Errirqsigen Register Bit Assignments
RM0082 RS_SDIO controller Table 644. ERRIRQSIGEN register bit assignments Name Reset value Type Description [15:14] VDSERSIGEN 1’h0 RW1C 1’b0 - Masked [13] CEATAERSIGEN 1’h0 RW1C 1’b1 - Enabled [12] TGTRESERSIGEN 1’h0 RW1C [11:10] Rsvd Reserved [09] ADMAERSIGEN [08] ACMD12ERSIGEN [07] CURLERSIGEN [06] DATAEBSIGEN...
Page 724: Table 646. Relation Between Auto Cmd12 Crc Error And Auto Cmd12 Timeout Error
RS_SDIO controller RM0082 Table 645. ACMD12ERSTS register bit assignments (continued) Name Reset value Type Description Occurs when detecting a CRC error in the command response. [02] ACMD12CRCER 1’h0 1’b0 - No Error 1’b1 - CRC Error Generated Occurs if the no response is returned. within 64 SDCLK cycles from the end bit of the command.
Page 725: Table 647. Cap1 Register Bit Assignments
RM0082 RS_SDIO controller The timing of changing Auto CMD12 Error Status can be classified in three scenarios: ● When the HC is going to issue Auto CMD12. – Set bit 0 to 1 if Auto CMD12 cannot be issued due to an error in the previous command.
Page 726 RS_SDIO controller RM0082 Table 647. CAP1 register bit assignments (continued) Reset Name Type Description value This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is logic ‘0’, the Suspend and Resume mechanism are not SUSRESSUP supported and the HD shall not issue either [23] 1’h1...
Page 727: Table 648. Cap2 Register Bit Assignments
RM0082 RS_SDIO controller Table 647. CAP1 register bit assignments (continued) Reset Name Type Description value This value indicates the base (maximum) clock frequency for the SD clock. Unit values are 1 MHz. If the real frequency is 16.5 MHz, the larger value shall be set 0x11 (17 MHz) because the HD uses this value to calculate the clock divider value and it shall not exceed the upper limit of the SD clock...
Page 728: Table 650. Maxcurr2 Register Bit Assignments
RS_SDIO controller RM0082 32.7.27 MAXCURR2 register The MAXCURR2 bit assignments are given in Table 650. Table 650. MAXCURR2 register bit assignments Reset Name Type Description value [31:00] Rsvd Reserved Table 651. Maximum current value definition Register value (decimal) Current value Get information through another method 4 mA 8 mA...
Page 729: Table 653. Feerrintsts Register Bit Assignments
RM0082 RS_SDIO controller Table 652. ACMD12FEERSTS register bit assignments (continued) Reset Name Type Description value Force Event for Auto CMD12 CRC Error. FEACMDCR [02] 1’h0 1’b1 - Interrupt is generated 1’b0 - no interrupt Force Event for Auto CMD12 timeout Error. [01] FEACMDTO 1’h0...
Page 730: Table 654. Admaerrsts Register Bit Assignments
RS_SDIO controller RM0082 Table 653. FEERRINTSTS register bit assignments (continued) Reset Name Type Description value Force Event for Current Limit Error [07] FECLER 1’h0 1’b1 - Interrupt is generated 1’b0 - No interrupt Force Event for Data End Bit Error [06] FEDATAEBER 1’h0...
Page 731: Table 655. Admaerrsts Bits[1:0] Definition
RM0082 RS_SDIO controller Table 654. ADMAERRSTS register bit assignments (continued) Reset Name Type Description value ADMA Length Mismatch Error This error occurs in the following 2 cases. While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block [02] ADMALMER...
Page 732: Table 656. Admaaddr Register Bit Assignments
RS_SDIO controller RM0082 Table 656. ADMAADDR register bit assignments Reset Name Type Description value This register holds byte address of executing command of the Descriptor table. 32 bit Address Descriptor uses lower 32 bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table.
Page 733: Table 659. Spiirqsupp Register Bit Assignments
RM0082 RS_SDIO controller Table 659. SPIIRQSUPP register bit assignments Reset Name Type Description value This bit is set to indicate the assertion of interrupts in the SPI mode at any time, irrespective of the [07:00] SPIIRQSUPP 8’h00 status of the card select (CS) line. If this bit is zero, then SDIO card can only assert the interrupt line in the SPI mode when the CS line is asserted.
Page 734 RS_SDIO controller RM0082 Table 661. HCTRLVER register bit assignments (continued) Reset Name Type Description value This Status indicates the Host Controller Spec Version. The Upper and Lower 4 bits indicate the version. 00 - SD Host Specification version 1.0 [07:00] 8’h02 Hwinit 01 - SD Host Specification version 2.00 including...
Page 735: Overview
RS_Color liquid crystal display controller (CLCD) 33.1 Overview Within the Reconfigurable Array Subsystem, SPEAr300 can provide an ARM PrimeCell® Color Liquid Crystal Display Controller (CLCD) that provides all the necessary control signals to interface directly to a variety of color and monochrome LCD panels.
Page 736: Number Of Colors Supported
RS_Color liquid crystal display controller (CLCD) RM0082 Programmable parameters are: ● Horizontal front and back porch ● Horizontal synchronization pulse width ● Number of pixels per line ● Vertical front and back porch ● Vertical synchronization pulse width ● Number of lines per panel ●...
Page 737: Figure 78. Clcd Block Diagram
RM0082 RS_Color liquid crystal display controller (CLCD) used and applied to all three colors components simultaneously. Refer to 33.4 & 33.5 signal descriptions for more information. Number of colors supported for color STN panels are: ● 1 bpp, palettized, 2 colors selected from 3375 ●...
Page 738: Table 662. Clcd Signal Interface
RS_Color liquid crystal display controller (CLCD) RM0082 33.3 Signal interfaces The CLCD directly interfaces with the signals summarized in Table 662. Table 662. CLCD signal interface Size Group Signal name Direction Description (bit) STN AC bias drive or TFT data enable CLAC Output output...
Page 739: Table 663. Lcd Stn Panel Signal Multiplexing
RM0082 RS_Color liquid crystal display controller (CLCD) Table 663. LCD STN panel signal multiplexing 4 bit mono 4 bit mono 8 bit mono 8 bit mono Color STN Color STN External STN single STN dual STN single STN dual single panel dual panel panel panel...
Page 740: Main Functions Description
RS_Color liquid crystal display controller (CLCD) RM0082 Table 664. LCD TFT panel signal multiplexing (continued) External pin TFT 24 bit TFT 18 bit CLD[19] BLUE[3] Reserved CLD[18] BLUE[2] Reserved CLD[17] BLUE[1] BLUE[4] CLD[16] BLUE[0] BLUE[3] CLD[15] GREEN[7] BLUE[2] CLD[14] GREEN[6] BLUE[1] CLD[13] GREEN[5]...
Page 741: Dual Dma Fifos And Associated Control Logic
RM0082 RS_Color liquid crystal display controller (CLCD) The inherent AMBA AHB master interface state machine performs the following functions: ● Loads the upper panel base address into the AMBA AHB address incrementor on recognition of a new frame. ● Monitors both the upper and lower DMA FIFO levels and asserts HBUSREQM to request display data from memory, filling them to above the programmed water mark.
Page 742: Table 665. Lblp, Dma Fifo Output Bit 31 To Bit 16
RS_Color liquid crystal display controller (CLCD) RM0082 Table 665. LBLP, DMA FIFO output bit 31 to bit 16 DMA FIFO Output Bits p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 Table 666. LBLP, DMA FIFO output bit15 to bit 0 DMA FIFO Output Bits p15 p14 p13 p12 p11 p10 Table 667.
Page 743: Table 668. Bbbp, Dma Fifo Output Bit15 To Bit 0
RM0082 RS_Color liquid crystal display controller (CLCD) Table 668. BBBP, DMA FIFO output bit15 to bit 0 (continued) DMA FIFO Output Bits Table 669. LBBP, DMA FIFO output bit 31 to bit 16 DMA FIFO Output Bits p24 p25 p26 p27 p28 p29 p30 p31 p16 p17 p18 p19 p20 p21 p22 p23 Table 670.
Page 744: Ram Palette
RS_Color liquid crystal display controller (CLCD) RM0082 Table 671. RGB Mode data format (continued) DMA FIFO 24 bit RGB 16 bit 1:5:5:5 RGB 16 bit 5:6:5 RGB 16 bit 4:4:4 RGB output bit [25] p1 - Green4 p1 - Green4 p1 - Blue1 [24] p1 - Green3...
Page 745: Table 672. Palette Data Storage
RM0082 RS_Color liquid crystal display controller (CLCD) For information on the numbers of colors supported, refer to Section 33.1.1: Number of colors supported The palette RAM is a dual port RAM with independent controls and addresses for each port. Port1 is used as a read/write port and is connected to the AMBA AHB slave interface. The palette entries can be written and verified through this port.
Page 746: Panel Clock Generator
RS_Color liquid crystal display controller (CLCD) RM0082 33.5.8 Panel clock generator The output of the panel clock generator block is the panel clock. This is a divided down version of CLCDCLK. It can be programmed in the range CLCDCLK/2 to CLCDCLK/33 to match the bpp data rate of the LCD panel.
Page 747: Bus Architecture
RM0082 RS_Color liquid crystal display controller (CLCD) 33.5.11 Bus architecture The CLCD incorporates a master and a slave interface. The master interface is directly connected to a memory controller with an AMBA AHB slave interface, while the slave interface is connected to the AMBA AHB bus. AMBA AHB supports a wide range of on-chip bus sizes, from eight bits up to 1 024 bits.
Page 748: Table 673. Clcd Configuration Registers
RS_Color liquid crystal display controller (CLCD) RM0082 Figure 79. Powering up and down sequences LCD On LCD Off Sequence Sequence Minimum 0 ms Minimum 0 ms Min 0 ms Min 0 ms CLLP,CLCP,CL FP,CLAC,CLLE CLPOWER, CLD[23:0] Mn(display Mn(display specific)mSec specific)mSec (Provided through SW) (Provided through SW) 33.6...
Page 749: Table 674. Color Palette Register
RM0082 RS_Color liquid crystal display controller (CLCD) Table 673. CLCD configuration registers (continued) Width Reset Name Offset Type Description (bit) value LCDMIS 0x24 5’h0 Mask interrupt status register LCDICR 0x28 5’h0 Interrupt clear register LCDUPCUR 0x2C undefined Upper panel current address value register LCDLPCUR 0x30 undefined Lower panel current address value register...
Page 750: Table 676. Lcdtiming0 Register Bit Assignments
RS_Color liquid crystal display controller (CLCD) RM0082 Table 676. LCDTiming0 register bit assignments Reset Name Description value Horizontal back porch is the number of CLCP periods between the falling edge of CLLP and the start of active data. Program with value minus 1. The 8 bit HBP field specifies the number of pixel clock periods inserted at the beginning of each line [31:24]...
Page 751: Table 677. Lcdtiming1 Register Bit Assignments
RM0082 RS_Color liquid crystal display controller (CLCD) Dual panel mode: ● HSW = 3 ● HBP = 5 ● HFP = 5 ● PCD = 5 (CLCDCLK/7). If sufficient time is given at the start of the line (for example, setting HSW = 6, HBP = 10), data is not corrupted for PCD = 4 (minimum value).
Page 752: Table 678. Lcdtiming2 Register Bit Assignments
RS_Color liquid crystal display controller (CLCD) RM0082 Table 677. LCDTiming1 register bit assignments (continued) Reset Name Description value Vertical synchronization pulse width is the number of horizontal synchronization lines. Must be small (for example, program to zero) for passive STN LCDs.
Page 753 RM0082 RS_Color liquid crystal display controller (CLCD) Table 678. LCDTiming2 register bit assignments (continued) Reset Name Description value Clocks per line. This field specifies the number of actual CLCP clocks to the LCD panel on each line. This is the number of PPL [25:16] 10’h0 divided by 1 for TFT, 4 or 8 for mono passive, or 2 2/3 for color...
Page 754: Table 679. Lcdtiming3 Register Bit Assignments
RS_Color liquid crystal display controller (CLCD) RM0082 Table 678. LCDTiming2 register bit assignments (continued) Reset Name Description value Lower five bits of panel clock divisor. The ten bit PCD field, comprising PCD_HI (bits [31:27]) and PCD_LO, is used to derive the LCD panel clock frequency CLCP from the CLCDCLK frequency, CLCP = CLCDCLK/(PCD+2).
Page 755: Table 680. Lcdupbase Register Bit Assignments
RM0082 RS_Color liquid crystal display controller (CLCD) They are read/write registers used to program the base address of the frame buffer. LCDUPBASE is used for: ● TFT displays ● Single panel STN displays ● The upper panel of dual panel STN displays. LCDLPBASE is used for the lower panel of dual panel STN displays.
Page 756: Table 683. Lcdcontrol Register Bit Assignments
RS_Color liquid crystal display controller (CLCD) RM0082 Table 682. LCDIMSC register bit assignments (continued) Reset Name Description value [01] FUFINTRENB 1’h0 FIFO underflow interrupt enable Reserved, do not modify, read as zero, write as [00] zero 33.6.10 LCD control register LCDControl is the control register.
Page 757: Lcdris Register
RM0082 RS_Color liquid crystal display controller (CLCD) Table 683. LCDControl register bit assignments (continued) Reset Name Description value RGB of BGR format selection: [08] 1’h0 1’b0 = RGB normal output 1’b1 = BGR red and blue swapped. LCD interface is dual panel STN: [07] LCDDUAL 1’h0...
Page 758: Table 684. Lcdris Register Bit Assignments
RS_Color liquid crystal display controller (CLCD) RM0082 Table 684. LCDRIS register bit assignments Reset Name Description value [13:05] AHB bus master error status. Set when the AHB [04] MBERROR 1’h0 master encounters a bus error response from a slave. Vertical compare. Set when one of the four vertical [03] VCOMP 1’h0...
Page 759: Table 686. Lcdicr Register Bit Assignments
RM0082 RS_Color liquid crystal display controller (CLCD) Table 686. LCDICR register bit assignments Reset Name Description value [31:05] Reserved, do not modify, write as zero [04] MBERROR 1’h0 Clear AHB Master errors interrupt. [03] VCOMP 1’h0 Clear vertical compare interrupt. [02] LNBU 1’h0...
Page 760: Table 690. Pheriphid0 Register Bit Assignments
RS_Color liquid crystal display controller (CLCD) RM0082 Table 689. LCDPalette register bit assignments (continued) Reset Name Description value [20:16] R[4:0] Red palette data. Intensity bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the [15] number of colors to 64K, where each color has two different intensities.
Page 761: Table 692. Pheriphid2 Register Bit Assignments
RM0082 RS_Color liquid crystal display controller (CLCD) Table 692. PHERIPHID2 register bit assignments Reset Name Description value [31:08] Reserved, read as zero [07:04] Revision 4’h0 These bits read back as 0x0 [03:00] Designer1 4’h4 These bits read back as 0x4 Table 693.
Page 762: Interrupts
RS_Color liquid crystal display controller (CLCD) RM0082 Table 697: PCELLIDID3 register bit assignments Name Reset Value Description [31:08] Reserved, read as zero [07:00] PCELLIDID3 8’hB1 These bits read back as 0xB1 33.7 Interrupts There are five interrupts generated by the CLCD. The following are individual maskable active HIGH interrupts: ●...
Page 763: Figure 80. Power Up & Power Down Sequences
RM0082 RS_Color liquid crystal display controller (CLCD) It is possible to clear the interrupt by writing a logic ‘1’ to the LNBU bit in the LCDICR Register. 33.7.4 CLCDFUFINTR The FIFO underflow interrupt is asserted when internal data is requested from an empty DMA FIFO.
Page 764: Figure 81. Clcd Clock Muxing Scheme
RS_Color liquid crystal display controller (CLCD) RM0082 33.8 CLCD clock scheme The CLCDCLK for the CLCD IP can be input from 2 sources. LCD Timing Register2 selects between HCLK and 48MHz clock. Figure 81. CLCD clock muxing scheme CLCD Controller AHB Slave only Interface bus for Controller programming Register Block...
Page 765: Table 698. Telecom Block Pin Signals
RS_Telecom IP RS_Telecom IP This section describes the telecom module. 34.1 Overview Within the Reconfigurable Array Subsystem, SPEAr300 provides a Telecom IP which has an AMBA 2 compatible interface and supports various telephony, audio applications. 34.2 Main features ● Voice transmission for normal telecommunications (TDM Interface).
Page 766: Figure 82. Telecom Block Diagram
RS_Telecom IP RM0082 Table 698. Telecom block pin signals (continued) Signal Direction Description I2S DOUT I2S Output SYNC(7:1) -OUT SYNC (7:0) Synchronizer Signals SYNC(0) -INOUT SPI_I2C (7:0) SPI Chip Select /I2C Clock IT (7:0) Interrupt bus G10 (10:0) INOUT GPIOs G8 (7:0) INOUT GPIOs...
Page 767: Figure 83. Tdm Clock Cell Block Diagram
RM0082 RS_Telecom IP The various sub blocks of Telecom IP are describes in the following sections:- 34.4.1 Regs and regs_rw blocks These blocks contain the set of telecom programming registers which are described in detail in the Programmer’s Model Section 34.5 34.4.2 TDM clock block The TDM clock block generates the clock in Master mode and recovers the clock in slave...
Page 768: Figure 84. Sync0 (Slave/Master) And Sync1 To Sync3 Possible Shaping
RS_Telecom IP RM0082 Internally, the master mode can select between four clock sources, then divide it or use as it is (for configuration please refer to Table 704: TDM_conf register (Offset 0x04)). The 16 bit divider allows division from 2 to 131072. ●...
Page 769: Figure 85. Sync4 To Sync7 Generation
RM0082 RS_Telecom IP Here below is shown the generation of SYNC4-SYNC7 for the first height bits of the frame; Successive bits are generated by successive words. Figure 85. SYNC4 to SYNC7 generation Byte3 Byte2 Byte1 Byte0 Word0 1 0 1 1 1 1 1 0 0xBEFE1C2E SYNC_7 SYNC_6...
Page 770: Action Memory
RS_Telecom IP RM0082 the DIN pin). Switching data is stored in a single port Switching Memory without access from AHB. ● Bufferization means that data from DIN pin (one to four timeslots per channel per frame) is stored in the buffer memory during a programmable number of frames (please refer to Table 717: TDM_Frame_NBR register (Offset 0x3C)) and data from buffer...
Page 771: Figure 87. Illustration For Tdm Switching
RM0082 RS_Telecom IP switching memory) is played on the DOUT pin. During TS511, TS511 received on the DIN pin is stored at the 511st byte of the storage part of the switching memory while TS3 of the previous frame (3rd byte of the reading part of the switching memory) is played on the TDM output, allowing a phone call to be established between the caller connected on TS3 and the one connected on TS511.
Page 772: Figure 89. Storage In Memory During An Even Switched Frame
RS_Telecom IP RM0082 Figure 89. Storage in memory during an even switched frame Switching Memory 2048*8 Memory IDM TX 34.4.7 Buffer memory Buffer memory allows bufferization of upto 16 channels. It contains two banks: ● one available for the TDM state machine, ●...
Page 773: Figure 90. Various Type Of Data Carried By The Tdm Bus
RM0082 RS_Telecom IP For Narrowband (8 kHz), Companded (8 bit) samples - The pointer will progress by 1 byte at each frame. For Narrowband, Linear (16 bits) samples - The pointer will progress by 2 bytes at each frame. The two bytes will be in consecutive time slots. For Wideband companded samples - The pointer will also progress by 2 bytes at each frame.
Page 774: Figure 92. Memory Filling After 3 Frames According Narrowband Cases
RS_Telecom IP RM0082 Figure 92. Memory filling after 3 frames according narrowband cases Byte3 Byte2 Byte1 Byte0 Byte3 Byte2 Byte1 Byte0 0000 MSB2 LSB2 MSB1 LSB1 MSB3 LSB3 03FF 3800 3EFF 3000 3FFF Odd bank Even bank 4000 43FF 7800 7EFF 7000 7FFF...
Page 775: Figure 93. Memory Filling After 3 Consecutive Frames For Two Wideband Cases
RM0082 RS_Telecom IP Figure 93. Memory filling after 3 consecutive frames for two wideband cases Byte3 Byte2 Byte1 Byte0 Byte3 Byte2 Byte1 Byte0 0000 MSB2 LSB2 MSB1 LSB1 MSB4 LSB4 MSB3 LSB3 MSB6 LSB6 MSB5 LSB5 03FF 3800 3EFF 3000 3FFF Odd bank Even bank...
Page 776: Figure 95. Sample Management On Even Frame
RS_Telecom IP RM0082 Figure 95. Sample management on even frame To/From 0000 Bank bit Channel Odd Buffer 3FFF 10 bits frame counter 4000 Even Buffer To/From offset bit offset bit 7FFF byte3 byte2 byte1 byte0 Type In case of buffering mode, on the TDM side, for a given channel, during frame n, first the sample of frame n (provided by CPU) is read on the DOUT line and then the input sample of frame n from DIN line is stored at the same place.
Page 777: Table 699. I2S Interface Pins
RM0082 RS_Telecom IP Figure 97. Buffer address generation Selected an the basis of number of samples given by [21:20]bits of the Action Memory register Offset Frame CPT Partial address Selected an the basis of number of samples given Channel 1 [26:24]bits of the Action Memory Bank bit...
Page 778: Figure 98. I2S Data Reception And Transmission (8 Bits)
RS_Telecom IP RM0082 The first three signals can be divided by the I2S_CLK block to adjust to the correct frequency. In slave mode, the clock will be received on I2S_CLK pin. ● Two banks are used to exchange the samples with the processor. The number of sample stored in a buffer is programmable (please refer to Table 722: I2S_CONF2 register (Offset...
Page 779: Figure 99. I2S Data Flow On 2*32 Bit Data
RM0082 RS_Telecom IP Figure 99. I2S data flow on 2*32 bit data I2S_LRCK Left Left Right Right 1 bit I2S_DIN Output Input Buffer Buffer 1000 0000 To and From Processor 07FF To and From 0800 Processor 1FFF 0FFF I2S_DOUT I2S_DIN 1 bit Left Left...
Page 780: Figure 100. Dac Application
RS_Telecom IP RM0082 Figure 100. DAC application 8 kHz input In this figure, 8 kHz input data is first over sampled by the 16 bit data processor to 64 kHz. Then the noise shaper will lead to an output signal of 2048 kHz by a 32* over sampling. Data at the input of the noise shaper can be optionally interpolated 64kHz output 32 bits...
Page 781: Table 700. Camera Interface Signal
● SPI-I2C block allows upto 8 SPI and I2C devices or codecs to share one I2C or SPI interface in fixed part of SPEAr300. ● SPI is a chip select bus and only one chip select signal is available. This block allows switching this signal to multiple devices.
Page 782: Figure 103. It Bus Change And Persistency Supervision
RS_Telecom IP RM0082 34.4.12 General purpose GPIOs G8 and G10 ● G8(7:0) and G10(9:0) are a set of eighteen general purpose GPIO provided primarily for SLIC management. ● G10(7:0) have an added capability of generating an interrupt on change of value or persistence of change similar to GPIO_IT bus.
Page 783: Table 701. Telecom Address Map
RM0082 RS_Telecom IP 34.5.1 Address map Table 701. Telecom address map Start Address End Address Name 0x5000_0000 0x5000_FFFF Register Set 0x5001_0000 0x5001_0FFF Action Memory 0x5003_0000 0x5003_7FFF Buffer Memory 0x5004_0000 0x5004_0FFF Sync Memory 0x5005_0000 0x5005_0FFF I2S Bank 1 0x5005_1000 0x5005_1FFF I2S Bank 2 34.5.2 Register set The base address of telecom registers is 0x5000_0000.
Page 784: Table 703. Boot Register (Offset 0X00)
RS_Telecom IP RM0082 Table 702. Telecom registers (continued) Offset Type Name 0x50 I2S_CLK_CONF 0x54 Interrupt mask 0x58 Interrupt status 0x6C I2S_CONF2 34.6 Description of registers This section describes the registers of telecom block. 34.6.1 Boot register Boot register is dedicated to the boot ROM software. The bits [15:00] are a Magic number 0x1C8C”.
Page 785: Table 704. Tdm_Conf Register (Offset 0X04)
RM0082 RS_Telecom IP RESET: all ‘0’ Table 704. TDM_conf register (Offset 0x04) Bits Name Comments loopback from DIN to DOUT (external) [31] LBio when LBio = ‘0’ no loopback is implemented when LBio = ‘1’ DOUT plays back the DIN value loopback from DOUT to DIN [30] LBoi...
Page 786 RS_Telecom IP RM0082 Table 704. TDM_conf register (Offset 0x04) (continued) Bits Name Comments Others reserved selection of the input source for the 7 bits divider 3’b000 3’b001 CLKSM (pin TDM_CLK) [21:19] Isrc 3’b010 ClkR_oscl 3’b011 ClkR_Synt(3) 3’b100 PL_Clk4 others reserved this value will be compared to the divider counter value.
Page 787: Table 705. Gpio8_Dir Register (Offset 0X08)
RM0082 RS_Telecom IP Figure 104. TDM CLK_GEN bits ‘0’ DIV 15-0 ClkR_Synt(3) ClkR_osc1 DIV_CPT PL_CLK4 (16bit) PL_CLK4 CLKSM Isrc2-0 bypass PL_GPIO CLKSM tck2 Int_CLK PL_CLK2 ‘0’ ‘0’ CLKo1-0 Int_CLK PL_CLK3 Internal_clock CLKo1-0 ‘0’ CLR_Pll2 PL_CLK1 ClkR_Synt(3) MIIC1-0 34.6.3 GPIO8_DIR register GPIO8_DIR informs about the direction of the GPIO8 register pins.
Page 788: Table 706. Gpio10_Dir Register (Offset 0X0C)
RS_Telecom IP RM0082 34.6.4 GPIO10_DIR register GPIO10_DIR informs about the direction of the GPIO10 register pins. RESET: all ‘1’ Table 706. GPIO10_DIR register (Offset 0x0C) Bits Name Comments [31:10] Reserved [09] Dir9 [08] Dir8 [07] Dir7 [06] Dir6 When Dirx=0, the relevant GPIOx pin is set as output [05] Dir5 When Dirx=1, the relevant GPIOx pin is set as input...
Page 789: Table 708. Gpio10_Out Register (Offset 0X14)
RM0082 RS_Telecom IP RESET: all ‘0’ Table 708. GPIO10_out register (Offset 0x14) Bits Name Comments [31:10] Reserved [09] Val9 [08] Val8 [07] Val7 [06] Val6 The bits to be out on the respective pins if they are in output [05] Val5 mode.
Page 790: Table 710. Gpio10_In Register (Offset 0X1C)
RS_Telecom IP RM0082 RESET: all ‘0’ Table 710. GPIO10_in register (Offset 0x1C) Bits Name Comments [31:10] Reserved [09] [08] [07] [06] [05] Latched value from the respective pins. [04] [03] [02] [01] [00] 34.6.9 IT-GEN register This register manages pin IT[7:0] or GPIO10_in [7-0]. It allows generating an interrupt when either a change appears on one pin, or when a change is stable for a persistency time given by PERS_time register.
Page 791: Gpiot Register
RM0082 RS_Telecom IP Table 711. IT_GEN register (Offset 0x24) (continued) Bits Name Comments 1 - Interrupt when 8 bits are stable for pers_time after last change on P6 [12] 0 - No interrupt on stability of change 1 - Interrupt on change on pin 5 [11] 0 - No interrupt on change on pin 5 1 - Interrupt when 8 bits are stable for pers_time after last...
Page 792: Table 712. Gpiot Register (Offset 0X28)
RS_Telecom IP RM0082 RESET: all ‘0’ Table 712. GPIOt register (Offset 0x28) Bits Name Comments [31:08] Reserved [07:00] Value of the IT pins latched by int_CLK 34.6.11 GPIOtt register In this register the processor can read the value of the GPIOt pins latched by the int_CLK clock (IT pins latched two times).
Page 793: Table 716. Tdm_Timeselot_Nbr Register (Offset 0X38)
RM0082 RS_Telecom IP RESET: all ‘0’ Table 716. TDM_timeselot_NBR register (Offset 0x38) Bits Name Comments [31:11] Reserved The number of timeslots in a frame. [10:00] 0 x 200 = 512 timeslots. 34.6.15 TDM_frame_NBR register This register informs about the number of samples that must be compiled in buffering mode before switching the banks and interrupting the processor.
Page 794 RS_Telecom IP RM0082 Table 718. TDM_SYNC_GEN register (Offset 0x40) (continued) Bits Name Comments Automatic buffer bank management: When ABBM = 0, the AHB delivers the full address for the buffer memory access. The processor then need to know which bank is available for it.
Page 795 RM0082 RS_Telecom IP Table 718. TDM_SYNC_GEN register (Offset 0x40) (continued) Bits Name Comments Informs if the frame synch (SYNC3) is for a delayed frame of non delayed frame When bdel3 = 0, the frame sync signal is aligned with the first [20] Bdel3 bit of the timeslot...
Page 796 RS_Telecom IP RM0082 Table 718. TDM_SYNC_GEN register (Offset 0x40) (continued) Bits Name Comments This bit informs if the PCM synchro (SYNC2) must be in wideband type (one additional pulse at the middle of the frame) When Wb2 = 0, the PCM carries narrowband data. Only one [13] pulse is required for the framesync (generally every 125µS).
Page 797 RM0082 RS_Telecom IP Table 718. TDM_SYNC_GEN register (Offset 0x40) (continued) Bits Name Comments These bits are used with Wb1 according to the following table Use1[1] Use1[0] Synchro type PCM/DSP-SFS [06:05] Use1 PCM wideband (SFS) Informs if the frame synch (SYNC0) is for a delayed frame of non delayed frame When bdel0 = 0, the frame sync signal is aligned with the first [04]...
Page 798: Table 719. Spi_I2C_Usage Register (Offset 0X44)
RS_Telecom IP RM0082 34.6.17 SPI_I2C_usage register RESET: all ‘0’ Table 719. SPI_I2C_usage register (Offset 0x44) Bits Name Comments [31:08] Reserved [07] [06] [05] when Ux=0, the switched signal is I2C_SCL [04] when Ux=1, the switched signal is SS0_SS [03] [02] [01] [00] 34.6.18...
Page 799: Table 721. I2S_Conf Register (Offset 0X4C)
RM0082 RS_Telecom IP RESET: all ‘0’ Table 721. I2S_CONF register (Offset 0x4C) Bits Name Comments When I2S_IT =1, an I2S interrupt is in progress (after bank [31] I2S_IT switching) [30:28] Reserved Read only bit. Indicates the I2S memory bank being accessed [27] BANK by the I2S block to allow the processor to be synchronized with...
Page 800 RS_Telecom IP RM0082 Table 721. I2S_CONF register (Offset 0x4C) (continued) Bits Name Comments Input data width. Only the valid bits will be shifted in the receive register and then right aligned. If this data needs to be left aligned in the memory, Tfs1-0 bits must be set. 8 bits [09:08] 16 bits...
Page 801: Table 722. I2S_Conf2 Register (Offset 0X6C)
RM0082 RS_Telecom IP Table 721. I2S_CONF register (Offset 0x4C) (continued) Bits Name Comments When M/S = '0' the device is slave and the pin I2S_CLK is an [01] input. When ACT = 0, the I2S cell is not used. No sample will be written/read in the memory that is available for the processor.
Page 802: Table 723. I2S_Clk_Conf Register (Offset 0X50)
RS_Telecom IP RM0082 Table 722. I2S_CONF2 register (Offset 0x6C) (continued) Bits Name Comments informs if an interrupt has to be generated when an address bit [03] IT_tog toggles from 0 to 1. Purpose of this bit is to generate an interrupt every N samples (N=2x), even if banks are greater.
Page 803 RM0082 RS_Telecom IP Table 723. I2S_CLK_CONF register (Offset 0x50) (continued) Bits Name Comments inversion of TDM_CLK when selected by intsel when invint =0, no action [23] Invint when invint =1, if TDM_CLK is selected by Intsel, it will be inverted before being sent to the I2S block. select the TDM clock instead of the I2S clock [22] Intsel...
Page 804: Table 724. Interrupt Mask Register (Offset 0X54)
RS_Telecom IP RM0082 Figure 105. I2S clock tree ‘0’ DIV 15-0 ClkR_Synt(2) ClkR_osc1 DIV_CPT PL_CLK1 (16bit) PL_CLK4 Isrc2-0 bypass CLKSM Clock Internal_clock tck2 I2S_CLK TCM_intCLK TCM_intCLK intsel CLKo0-1 Int_I2S_CLK to I2S interface 34.6.22 Interrupt mask register RESET: all ‘0’ Table 724. Interrupt mask register (Offset 0x54) Bits Name Comments...
Page 805: Table 725. Dummy Access Address
RM0082 RS_Telecom IP Bit is 1: Interrupt is unmasked The request will be cleared by a dummy access (read or write) of a byte at the following addresses: Table 725. Dummy access address Interrupt Dummy Access Address (byte) 0x5006_0000 ITch 0x5006_0001 ITi2S 0x5006_0002...
Page 806: Table 727. Action Memory
RS_Telecom IP RM0082 Table 726. Interrupt status register (Offset 0x58) (continued) Bits Name Comments [11:09] Reserved [08] IT_GPIO [07] IT_KB [06] Reserved [05] Reserved Interrupt requests from IPs after filtering through interrupt mask register. [04] Reserved [03] ITtdm [02] ITi2s [01] ITch [00]...
Page 807 RM0082 RS_Telecom IP Table 727. Action memory (continued) Bits Name Comments Indicates how many channels are present. This further implies how many valid bits of Ch[3:0] are used to indicate the channel number in the action memory. It should be the same for all the active channels.
Page 808: Int Block
RS_Telecom IP RM0082 Table 727. Action memory (continued) Bits Name Comments This bit is used to inform that the last timeslot is switched on timeslot 0. As there is no time to store it in the memory and read back, the sample will go directly from the shift-in register to the shift-out register.
Page 809: Figure 106. Interrupt Management
RM0082 RS_Telecom IP Figure 106. Interrupt management KeyB GPIO Int_ITp Dummy read byte@50060000 ITch Int_ITch Dummy read byte@50060001 Int_ITi2 ITi2 To interrupt Ch0 Dummy read byte@50060002 Int_ITtdm ITtdm Dummy read byte@50060003 ITcaml Int_ITcaml Dummy read byte@50060004 ITcam Int_ITcam Dummy read byte@50060005 ITcamv Int_ITcamv Dummy read byte@50060006...
Page 810: Figure 107. Keyboard Controller Block Diagram
RM0082 RS_Keyboard controller 35.1 Overview Within its Reconfigurable Array Subsystem, SPEAr300 provides a GPIO/Keyboard block which is a two-mode input and output port. In summary, it provides: ● 18 bit general-purpose parallel port with input or output single pin programmability.
Page 811: Table 728. External Signals
RM0082 RS_Keyboard controller 35.2.2 Keyboard interface When Keyboard mode is selected, it is possible to read from APB Bus the value of externally connected keyboard, scanned at programmed rate. The keyboard may contain up to 81 keys. 18 port pins provide a 9x9 scanning matrix. 9 of the pins are strobes and nine (9) of the pins are inputs.
Page 812: Table 729. Register Map
RS_Keyboard controller RM0082 Table 728. External signals (continued) Port pin GPIO Keyboard COLUMN6 GPIO 15 input kbd(column)6 COLUMN7 GPIO 16 input kbd(column)7 COLUMN8 GPIO 17 input kbd(column)8 35.3.2 Register map The GPIO/Keyboard block can be fully configured by programming its registers which can be accessed at the base address 0xA000_0000.
Page 813: Table 731. Gpiodirreg Register Bit Assignments
RM0082 RS_Keyboard controller 35.3.3.2 GPIODIRREG register When GPIO Mode is enabled, the value in this register specifies whether the particular I/O pin is an output or not. Writing a logic1 to the register bit sets the port pin to output mode; otherwise the related pin is considered as only input.
Page 814: Table 734. Kbreg Register Bit Assignments
RS_Keyboard controller RM0082 Table 733. STATUSREG register bit assignments (continued) Reset Name Type Description value This bit is set to ‘1’ when a new keyboard value is available in KBREG. [01] KBNEWDATA 1’h0 Once data is read from KBREG, this bit should be reset to '0'.
Page 815: Rs_General Purpose Input Output (Gpio)
RM0082 RS_General Purpose Input Output (GPIO) RS_General Purpose Input Output (GPIO) Please refer to Chapter 18: BS_General purpose input/output (GPIO) for general details of this IP. 36.1 Application Notes Eight individually programmable input/output pins are available (instead of only 6 as in the fixed part GPIO block described in Chapter 17).
Page 816: Power And Clock Management
Power and clock management RM0082 Power and clock management 37.1 Overview Power consumption is an important design aspect of any modern system. Power management techniques allows to reduce power consumption ensuring requested performance by utilization. 37.1.1 Power management techniques System Control State Machine is a device feature designed to support reduction of power consumption controlling clock inputs to the CPU.
Page 817: Table 736. Power State For Synchronous Dram System (Dram Clocked By Pll1)
RM0082 Power and clock management This technique is easier from a designer prospect for software development and offer a well known consumption. It is recommended that when performance required is without critical task and it is sufficient to guarantee an average power computation. 37.2 System control state machine System control state machine is used to select the input frequency to apply to the system.
Page 818: Table 737. Power State For Asynchronous Dram System (Dram Clocked By Pll2)
Power and clock management RM0082 Table 737. Power state for asynchronous DRAM system (DRAM clocked by PLL2) Possible code State ARM clock DRAM execution memory Hibernate Self refresh None SLEEP Hibernate Active None Running RTC Osc. Self refresh Internal memory Internal memory and Running RTC Osc...
Page 819: Doze (Reset State)
RM0082 Power and clock management 37.2.2 DOZE (reset state) DOZE is the first state activated after reset. In this state CPU is running with RTC or MAIN Oscillator, according to bit set in PRPH_CLK_CFG.rtc_disable. After reset MAIN Oscillator is selected (that allows to have systems without RTC Oscillator).
Page 820: Table 738. Techniques Applicable In Normal State
Power and clock management RM0082 Table 738. Techniques applicable in NORMAL state Technique Synchronous DRAM Asynchronous DRAM Dynamic Frequency Scalling (DFS) Denied Allowed Dynamic Clock Switching (DCS) Allowed Allowed Combining DFC+DCS Denied Allowed Statically Frequency Selection and Clock Allowed Allowed Switching OFF 37.3 Dynamic frequency scaling...
Page 821: Table 739. Modules Supporting Dcs Technique
RM0082 Power and clock management Table 739. Modules supporting DCS technique Module Module Module GPIO SDRAM UART USB 2.0 host ARM subsystem USB 2.0 device Timer 2 Ethernet Timer 3 Flash serial (SMI) IrDA PLL1 Internal ROM JPEG codes PLL2 PLL3 37.5 Combining...
Page 822: Figure 109. Clock Supply
Power and clock management RM0082 Figure 109. Clock supply SPEAr320 JTAG/ETM9 ARM subsystem Timer ARM926EJS Basic subsystem 32kI/32kD cache Coprocessor System Int.Ctrl GPIO TCM -I/D Ctrl 8 chan. Flash serial 32KB SDRAM GPIO Ctrl DDR1 - 2 Misc. < < 5-23 <...
Page 823: Figure 110. Typical Power Consumption With Ddr2 @ 333 Mhz
RM0082 Power and clock management Figure 110. Typical power consumption with DDR2 @ 333 MHz Note: Slow, Doze and Sleep mode values are obtained with USB ports in suspend mode and then power off USB PLL (PLL3) (setting register USB2_PHY_CFG.PLL-pwdn to 1) Figure 111.
Page 824: Table 740. Power And Current Consumption For Modules
Power and clock management RM0082 The following information provides details about the condition under which values could be obtained: ● Data based on characterization, results tested at nominal VDD ● Several STD selected SPEAr revision B, tested on the device demoboard with external power supply dedicated to SPEAr ●...
Page 825: Table 742. Ip Voltage Usage
RM0082 Power and clock management Note: Values reported are related to a system in NORMAL state setting in asynchronous mode, DRAM clocked by PLL2 at 333 MHz Absolute value in bold delta values in normal 37.8.2 IPs power All IPs are connected to Vcore (1.2Volt) to power the I/F logic with the internal buses, some IPs are also connected to other voltages.
Page 826: Table 743. Booting Types
RM0082 BootROM BootROM is a small piece of code that starts its execution just after the SoC exits from reset. The following are the features supported by SPEAr300 BootROM: ● Boot from NOR serial Flash ● Boot from NAND Flash ●...
Page 827: Figure 112. Boot Stages
RM0082 BootROM Figure 112. Boot stages After exiting the reset state, the ARM runs the Boot ROM code. 1) In case of flash booting, it will copy a second level boot code from flash to the internal SRAM (Shadow memory) and jumps into it.
Page 828: Figure 113. Hardware Memory
BootROM RM0082 38.3 Hardware overview Figure 113. Hardware memory SPEAr300 50030000h D2800000h Shadow RAS Area NAND/ Memory FLASHES eSRAM eRAM Power On Reset FFFF0000h Boot ROM SDRAM (DDR2) High Vectors eROM 38.3.1 eROM (Embedded ROM) eROM is the 32KB of area starting from 0xFFFF_0000. The ARM processor is mapped to HIGH vectors and starts executing instructions from 0xFFFF_0000.
Page 829: Software Overview
RM0082 BootROM 38.4 Software overview This section describes the BootROM software for SPEAr300. 38.4.1 ARM processor modes SPEAr BootROM runs in supervisor mode during entire execution. 38.4.2 SoC peripheral interrupts SPEAr BootROM runs with all interrupts disabled, except in the particular case of boot/upgrade through USB, in which case it enable the USB interrupt.
Page 830: Boot Flows
BootROM RM0082 Compare the Image Name in received header with: – XLOADER in case of X-Loader – UBOOT in case of U-boot Compare the magic number in received header with 0x2705_1956. Checking the CRC of the image header and image received with the CRCs present in the header.
Page 831: Figure 114. Boot Flows
RM0082 BootROM Figure 114. Boot flows Start Initialize interrupts SMI initialization BootROM Jump to load address bypass? Test boot type Proceed to specific boot Booting Jump to X - loader/ U - Boot Success? Infinite loop 38.5.1 Serial NOR Flash boot In NOR Boot, BootROM tries to perform BootROM bypass i.e.
Page 832: Figure 115. Serial Nor Flash Boot
BootROM RM0082 Figure 115. Serial NOR Flash boot BootROM Jump to U - boot bypass U - boot present in first (ih_load + 0x40) sector of flash Failed Authenticate X - Loader? USB boot Passed Copy X - Loader from flash to shadow memory Jump (at ih_load) to X - Loader in shadow memory 38.5.2 NAND Flash boot...
Page 833: Figure 116. Nand Flash Boot
RM0082 BootROM Figure 116. NAND Flash boot Notes: Initialize FSMC controller for NAND 1) Check device id, if it is 8 bit, then proceed. 2) Else jump back to FSMC Read device ID code initialize and try for 16 bit NAND boot Compare ID and fill device descriptor Notes:...
Page 834: Table 744. Command Format
BootROM programs PLL1 to 333 MHz and system to Normal mode i.e. ARM frequency at 333 MHz, initializes UDC Controller and initializes USB state machine to GET_CMD phase. UDC supports 2 modes of operation i.e. Slave mode and DMA mode, in SPEAr300 BootROM UDC is configured in slave mode.
Page 835: Table 745. Device Descriptors
RM0082 BootROM Device Descriptors: - Each gadget has one device descriptor Table 745. Device descriptors Offset Field Size Value bLength Byte 0x12 bDescriptorType Byte 0x01 bcdUSB Word 0x200 bDeviceClass Byte 0x00 bDeviceSubClass Byte 0x00 bDeviceProtocol Byte 0x00 wMaxPacketSize0 Byte 0x40 idVendor Word 0x0483...
Page 836: Table 747. Interface Registers
BootROM RM0082 Table 747. Interface registers Offset Field Size Value bLength Byte 0x09 bDescriptorType Byte 0x04 bInterfaceNumber Byte 0x00 bAlternateSetting Byte 0x00 bNumEndpoints Byte 0x02 bInterfaceClass Byte 0x00 interfaceSubClass Byte 0x00 bInterfaceProtocol Byte 0x02 iInterface Byte 0x01 Endpoint descriptors:- A device supports the following endpoints. Bulk OUT endpoint:- Used for transfer of data from host to device.
Page 837: Table 750. String Descriptors
RM0082 BootROM String descriptors Table 750. String descriptors Offset Field Size Value bLength Byte 0x04 bDescriptorType Byte 0x03 bEndpointAddress Byte 0x0409 Doc ID 018672 Rev 1 837/844...
Page 838: Figure 117. Usb Boot
BootROM RM0082 Figure 117. USB boot System initialization to Normal mode Initialize UDC controller Initialize USB state machine (GET_CMD) Wait for command on BULK out End point 2 from USB host Decode the command Receiving Change state machine (GET_DATA) DDR driver Wait for expected number of bytes from Host.
Page 839: Serial (Uart) Boot
RM0082 BootROM 38.5.4 Serial (UART) Boot Serial boot initializes the UART IP and uses the X-modem protocol to receive the X-Loader image at a fixed baud rate of 11250 bits per second (bps). It then runs the X-Loader image which initializes the PLLs and DDR and then returns back the control to Boot code. After this, X-modem protocol is again used to download the U-boot image into DDR and then the image is run from there.
Page 840: Figure 118. Serial Boot
BootROM RM0082 Figure 118. Serial boot Initialize UART Receive X - Loader through X - modem protocol Failed Authenticate X - Loader? Passed Run X - Loader from eSRAM area Return to BootROM Receive U - boot through X - modem protocol Failed Authenticate U - boot?
Page 841: Ethernet Boot
RM0082 BootROM 38.5.5 Ethernet boot The Ethernet boot is specifically used to boot the devices which do not have a storage capacity. There are two phases in this kind of booting. For any device to communicate in an IP network, it needs to have an IP of its own. This can be a fixed IP which is stored in a non- volatile memory within the device or a new IP can be obtained through BOOTP server.
Page 842: Figure 119. Ethernet Boot
BootROM RM0082 Figure 119. Ethernet boot Initialize Ethernet Notes: - 1) DHCP timeout is 5 seconds Take IP through DHCP IP Received Notes: - 1) TFTP timeout is 5 seconds Receive X - Loader through TFTP Authenticate X - Loader? Failed Passed Run X - Loader and return...
Page 843: Table 751. Document Revision History
RM0082 Document revision history Document revision history Table 751. Document revision history Date Revision Changes 29-Apr-2011 Initial Release Doc ID 018672 Rev 1 843/844...
Page 844 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

STMicroelectronics SPEAr300 Reference Manual

Acronyms

Preface

Reference Documentation

Product Overview

Pin Description

Memory Map

CPU Subsystem_Arm926Ej-S

CPU Subsystem_Vectored Interrupt Controller (VIC)

Bus Interconnection Matrix

DDR Memory Controller (MPMC)

Quick Links

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Questions and answers

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Summary of Contents for STMicroelectronics SPEAr300