Table 566. Tx Event Fifo Configuration Field Description - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
[0:1]
[2:7]
EFWM
[8:9]
[10:15]
EFS
[16:29]
EFSA
[30:31]
44.3.5.2.42 Tx Event FIFO Status Register (TXEFS)
Address: 0x00F4
0 1
R
W
Reset 0 0
16 17 18
R 0
W
Reset 0 0
Field
[0:5]
6
TEFL
7
EFF
[8:10]

Table 566. Tx Event FIFO Configuration field description

Reserved.
Event FIFO Watermark.
0 Watermark interrupt disabled
1–32 Level for Tx Event FIFO watermark interrupt (IR[TEFW])
>32 Watermark interrupt disabled
Reserved.
Event FIFO Size.
0 Tx Event FIFO disabled
1–32 Number of Tx Event FIFO elements
>32 Values greater than 32 are interpreted as 32
The Tx Event FIFO elements are indexed from 0 to EFS - 1
Event FIFO Start Address.
Start address of Tx Event FIFO in Message RAM (32-bit word
Reserved.
2 3 4 5
0
0 0 0 0
19 20 21
EFGI
0 0 0 0
Figure 512. Tx Event FIFO Status register
Table 567. Tx Event FIFO Status field description
Reserved.
Tx Event FIFO Element Lost.
This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset.
0No Tx Event FIFO element lost
1Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
Event FIFO Full.
0Tx Event FIFO not full
1Tx Event FIFO full
Reserved.
Description
6 7 8 9
TEFL EFF 0
0 0 0 0
22 23 24 25
0
0 0 0 0
Description
DocID027809 Rev 4
CAN Subsystem
address,Figure
10 11 12 13
EFPI
0 0 0 0
26 27 28 29
EFFL
0 0 0 0
514.)
Access: R
14 15
0 0
30 31
0 0
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