Table 478. Gtmdi_Aru_Wpc1 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
ARU Debugging Channel 0 Data Activity Selection 1. The TSS1 bit selects the type of data activity
to monitor on ARU Debugging Channel 0.
28
0 Any Data (do not compare data). Watchpoint generation is based on a valid data indication on
TSS1
ARU Debugging Channel 0
1 Compare data with expected value
Halt Enable 1. The HEN1 Halt Enable 1 bit controls if the ARU Debugging Channel 0 is enabled to
HALT the GTM module. If this bit is set and an event occurs on the ARU Debugging Channel 0, a
23
Halt signal is generated to the GTM which enters debug state.
HEN1
0 Disables Halt GTM
1 Enables Halt GTM
Watchpoint Message Control 1. The WMC1 Watchpoint Message Control 1 bit controls the
watchpoint message sent through the Message Data bus. If this bit is set it enables valid matches
on the ARU Debugging Channel 0 to generate a watchpoint message. This bit is written by the
22
JTAG interface but can also be controlled at SoC level with dedicated Start/Stop signals inputs to
WMC1
GTMDI.
0 Watchpoint Messages disabled
1 Watchpoint Messages enabled
ARU Debugging Channel 1 Data Activity Selection. The TSS2 bit selects the type of data activity to
monitor on the ARU Debugging Channel 1.
12
0 Any Data (do not compare data). Watchpoint generation is based on a valid data indication on
TSS2
ARU Debugging Channel Monitor 1
1 Compare data with expected value
Halt Enable 2. The HEN2 Halt Enable 2 bit controls if the ARU debugging Channel 1 is enabled to
HALT the GTM module. If this bit is set and an event occurs on the ARU Debugging Channel 1, a
7
Halt signal is generated to the GTM which enters Halt state.
HEN2
0 Disables Halt GTM
1 Enables Halt GTM
Watchpoint Message Control 2. The WMC2 Watchpoint Message Control 2 bit controls the
watchpoint message sent through the Message Data bus. If this bit is set it enables match on the
6 ARU Debugging Channel 1 to generate a watchpoint message. This bit is written by the JTAG
interface but can also be controlled at SoC level with dedicated Start/Stop signals inputs to GTMDI.
WMC2
0 Watchpoint Messages disabled
1 Watchpoint Messages enabled
42.5.1.21 ARU watchpoint control 2 register (GTMDI_ARU_WPC2)
The GTMDI_ARU_WPC2 register shown in
issued by ARU Debugging Channels. These triggers are used for GTM to enter Halt state,
generate watchpoint messages and control logic external to GTMDI, such as in the SPU
interface.

Table 478. GTMDI_ARU_WPC1 field descriptions

DocID027809 Rev 4
GTM Development Interface (GTMDI)
Description
Figure 425 controls the Watchpoint Triggers
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