Dedicated Rx Buffers - STMicroelectronics SPC572L series Reference Manual

RM0400
44.3.10.2 Rx FIFOs
Rx FIFO 0 and Rx FIFO 1 can be configured to hold up to 64 elements each. Configuration
of the two Rx FIFOs is done via registers RXF0C and RXF1C. Received messages that
passed acceptance filtering are transferred to the Rx FIFO as configured by the matching
filter element. For a description of the filter mechanisms available for Rx FIFO 0 and Rx
FIFO 1 see
Section 44.3.6.1: Rx Buffer and FIFO
When an Rx FIFO full condition is signaled by IR[RFnF], no further messages are written to
the corresponding Rx FIFO until at least one message has been read out and the Rx FIFO
Get Index has been incremented. In case a message is received while the corresponding
Rx FIFO is full, this message is discarded and interrupt flag IR.RFnL is set. To avoid an Rx
FIFO overflow, the Rx FIFO watermark can be used. When the Rx FIFO fill level reaches the
Rx FIFO watermark configured by RXFnC[FnWM], interrupt flag IR[RFnW] is set. When
reading from an Rx FIFO, four times the Rx FIFO Get Index RXFnS[FnGI] has to be added
to the corresponding Rx FIFO start address RXFnC[FnSA].
44.3.11

Dedicated Rx Buffers

The M_CAN supports up to 64 dedicated Rx Buffers. The start address of the dedicated Rx
Buffer section is configured via RXBC.RBSA.
For each Rx Buffer a Standard or Extended Message ID Filter Element with SFEC / EFEC =
"111" and SFID2 / EFID2[10:9] = "00" has to be configured (see <Cross
Refs>Section 44.3.6.4, "Standard message ID filter element and <Cross
Refs>Section 44.3.6.5, "Extended message ID filter element).
After a received message has been accepted by a filter element, the message is stored into
the Rx Buffer in the Message RAM referenced by the filter element. The format is the same
as for an Rx FIFO element. In addition the flag IR.DRX (Message stored in Dedicated Rx
Buffer) in the interrupt register is set.
Filter Element
0
1
2
After the last word of a matching received message has been written to the Message RAM,
the respective New Data flag in register NDAT1,2 is set. As long as the New Data flag is set,
the respective Rx Buffer is locked against updates from received matching frames. The New
Data flags have to be reset by the Host by writing a '1' to the respective bit position.
While an Rx Buffer's New Data flag is set, a Message ID Filter Element referencing this
specific Rx Buffer will not match, causing the acceptance filtering to continue. Following
Message ID Filter Elements may cause the received message to be stored into another Rx
Buffer, or into an Rx FIFO, or the message may be rejected, depending on filter
configuration.
Section 44.3.10.1: Acceptance
Table 575. Example Filter Configuration for Rx buffers
SFID1[10:0]
EFID1[28:0]
ID debug message 1
ID debug message 2
ID debug message 3
DocID027809 Rev 4
filtering. The Rx FIFO element is described in
element.
SFID2[10:9]
EFID2[10:9]
00
00
00
CAN Subsystem
SFID2[5:0]
EFID2[5:0]
00 0000
00 0001
00 0010
1067/2058
1091