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RM0400
56.3.2.10
SAFE
Mode Configuration Register (ME_SAFE_MC)
Address 0x028
0
1
2
R
0
PWRLVL
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
Figure 967. SAFE Mode Configuration Register (ME_SAFE_MC)
This register configures system behavior during
details.
Note:
Byte write accesses are not allowed to this register.
56.3.2.11
DRUN
Mode Configuration Register (ME_DRUN_MC)
Address 0x02C
0
1
2
R
0
PWRLVL
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
Figure 968. DRUN Mode Configuration Register (ME_DRUN_MC)
This register configures system behavior during
details.
Note:
Byte write accesses are not allowed to this register.
Note:
The XOSCON configuration value is set according to the chip configuration:
3
4
5
6
0
0
0
0
0
0
0
19
20
21
22
0
0
0
0
0
0
0
0
3
4
5
6
0
0
0
0
0
0
0
19
20
21
22
0
0
0
0
0
0
0
0
DocID027809 Rev 4
Access: User read, Supervisor read/write, Test read/write
7
8
9
10
0
0
0
PDO
0
1
0
0
23
24
25
26
0
0
0
0
0
0
SAFE
mode. Please refer to
Access: User read, Supervisor read/write, Test read/write
7
8
9
10
0
PDO
0
0
0
0
0
0
23
24
25
26
0
0
0
0
0
0
DRUN
mode. Please refer to
Mode Entry Module (MC_ME)
11
12
13
14
0
0
1
0
0
27
28
29
30
SYSCLK
1
0
0
Table 928
11
12
13
14
0
0
1
0
0
27
28
29
30
SYSCLK
1
0
0
Table 928
15
FLAON
1
1
31
0
0
for
15
FLAON
1
1
31
0
0
for
1617/2058
1644
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