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Another difference is that only the PASS_LOCK3_PGn register for each password group is
used:
•
PASS_LOCK3_PG0
•
PASS_LOCK3_PG1
•
PASS_LOCK3_PG2
•
PASS_LOCK3_PG3
Note:
The mappings of PASS_LOCK3_PGn register bits to flash blocks vary with different
microcontrollers. See the flash memory section in the Device Configuration chapter of this
reference manual for the mappings specific to the SPC572Lx microcontroller.
The next sections discuss implementing secure read protection and overriding secure write
protection.
31.4.1
Implementing secure read protection
Implementation of secure read protection is done during initial flash setup as follows:
1.
Four 256-bit passwords (passwords 0–3) are stored in a protected OTP area of device
flash named UTEST flash. Each password secures a set of registers in the PASS
module (PASS_LOCK0_PGn–PASS_LOCK3_PGn) that have the same mapping of
register bits to flash blocks as the flash module's SEL0–3 registers and LOCK0–3
registers. These are the same passwords used by secure write protection and other
secure functions. The passwords are only created once.
2.
DCF records must be created to define which flash memory blocks are to be locked.
Those records determine the reset values of the PASS_LOCK3_PGn registers.
Like the other PASS_LOCKx_PGn registers, the PASS_LOCK3_PGn registers have
two functions.
–
–
The layout of the PASS_LOCK3_PGn registers is shown in
to implementing secure read protection are RL2–RL0.
.
0x010C LOCK3_PG0
0x011C LOCK3_PG1
Offset
0x012C LOCK3_PG2
0x013C LOCK3_PG3
0
1
R
PGL DBL
MO
W
(1)
2
Reset x
x
x
16
17
18
R
W
2
2
Reset
x
x
x
1. Reset value depends on life cycle. If life cycle is Customer delivery or earlier, the value will be 0, otherwise 1.
Reading the registers provides a lock status for each Read Locking group.
Changing the value of a mapped bit in a register changes the read protect status
of the corresponding Read Locking group.
2
3
4
5
0
MSTR
2
0
1
1
19
20
21
2
2
2
2
x
x
x
Figure 292. PASS_LOCK3_PGn Register
DocID027809 Rev 4
Flash Memory Programming and Configuration
6
7
8
9
0
0
1
1
0
0
22
23
24
25
256LCK_U
2
2
2
2
x
x
x
x
Figure
292. The fields relevant
Access: Read/Write
10
11
12
13
0
RL4
RL3
RL2
2
2
2
0
x
x
x
26
27
28
29
2
2
2
2
x
x
x
x
14
15
RL1
RL0
2
2
x
x
30
31
2
(2)
x
x
667/2058
673
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