Table 289. Pflash Calibration Region Descriptor N, Word 0 Description - STMicroelectronics SPC572L series Reference Manual

Flash memory controller (PFLASH Controller)
28.4.1.6 PFlash Calibration Region Descriptor n (PFCRDn)
Each 96-bit (12 byte) region descriptor specifies an overlay region where a flash access can
be remapped during calibration and debug. The calibration remap descriptors are organized
sequentially as 128-bit (16 byte) structures in the Platform Flash Controller's programming
model. Each of the three 32-bit words that define a single calibration region are detailed in
the subsequent sections; the fourth word is unused.
28.4.1.6.1 PFlash Calibration Region Descriptor n, Word0 (PFCRDn.Word0)
The first word of the flash memory controller overlay region descriptor defines the 0-modulo-
size logical start (byte) address of the calibration remap region. It is software's responsibility
to guarantee the low-order bits of the address, as defined by the remap descriptor size, are
zeroed to enable the remap descriptor hit logic to function correctly.
Successful writes to this word clear the calibration remap descriptor's valid bit.
.
Offset 0x100 + (16*n) + 0x00
0 1
R
W
Reset 0 0
16 17 18
R
W
Reset 0 0
Figure 245. PFlash Calibration Region Descriptor n, Word0 (PFCRDn.Word0)

Table 289. PFlash Calibration Region Descriptor n, Word 0 description

Name
0–27
LSTARTADDR
28.4.1.6.2 PFlash Calibration Region Descriptor n, Word1 (PFCRDn.Word1)
The second word of the flash memory controller calibration region descriptor defines the 0-
modulo-size byte physical start (byte) address of the calibration remap region. The contents
of this word define the targeted destination overlay memory. It is software's responsibility to
guarantee the low-order bits of the address, as defined by the remap descriptor size, are
zeroed to enable the remap descriptor hit logic to function correctly.
Successful writes to this word clear the calibration remap descriptor's valid bit.
576/2058
2 3 4 5
0 0 0 0
19 20 21
0 0 0 0
Logical Start Address. This field defines the most significant bits of the 0-modulo-size
logical start address of the overlay remap region. It corresponds to the logical system
address which maps to the flash memory space. Any write to PFCRDn.Word{0,1,2} clears
the corresponding PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid.
DocID027809 Rev 4
6 7 8 9
LSTARTADDR
0 0 0 0
22 23 24 25
LSTARTADDR
0 0 0 0
Description
Access: Supervisor
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
RM0400
Read/Write
14 15
0 0
30 31
0 0