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STMicroelectronics STM32F05 series Reference Manual

STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus

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Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F05xxx microcontroller memory and peripherals.

The STM32F05xxx is a family of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

corresponding datasheet.

For information on the ARM C

reference manual.

Table 1.

Microcontrollers

Related documents

■

Cortex-M0 technical reference manual, available from:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/

DDI0432C_cortex_m0_r0p0_trm.pdf

■

STM32F05xxx datasheets available from your nearest ST sales office.

April 2012

STM32F05xxx advanced ARM-based 32-bit MCUs

ORTEX

Applicable products

Type

Doc ID 018940 Rev 1

Reference manual

™-M0 core, please refer to the Cortex-M0 technical

STM32F051x4, STM32F051x6 , STM32F051x8

RM0091

Part numbers

www.st.com

1/742

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Summary of Contents for STMicroelectronics STM32F05 series

Page 1: Table 1. Applicable Products
RM0091 Reference manual STM32F05xxx advanced ARM-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32F05xxx microcontroller memory and peripherals. The STM32F05xxx is a family of microcontrollers with different memory sizes, packages and peripherals.
Page 2: Table Of Contents
Contents RM0091 Contents Documentation conventions ....... . . 34 List of abbreviations for registers ....... 34 Glossary .
Page 3 RM0091 Contents 3.5.8 Write protection register (FLASH_WRPR) ..... . . 58 Flash register map ......... . 58 Option byte description .
Page 4: Syscfg External Interrupt Configuration Register
Contents RM0091 Reset and clock control (RCC) ....... . 82 Reset .
Page 5 RM0091 Contents GPIO introduction ......... . 118 GPIO main features .
Page 6 Contents RM0091 9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) ........136 9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) .
Page 7 RM0091 Contents 11.1.3 Interrupt and exception vectors ......157 11.2 Extended interrupts and events controller (EXTI) ....159 11.2.1 Main features .
Page 8 Contents RM0091 12.5.3 End of conversion, end of sampling phase (EOC, EOSMP flags) ..180 12.5.4 End of conversion sequence (EOSEQ flag) ..... 180 12.5.5 Example timing diagrams (single/continuous modes .
Page 9 RM0091 Contents 13.3.2 DAC output buffer enable ........207 13.3.3 DAC data format .
Page 10 Contents RM0091 15.3 TIM1 functional description ........225 15.3.1 Time-base unit .
Page 11 RM0091 Contents 15.4.15 TIM1 capture/compare register 2 (TIM1_CCR2) ....285 15.4.16 TIM1 capture/compare register 3 (TIM1_CCR3) ....285 15.4.17 TIM1 capture/compare register 4 (TIM1_CCR4) .
Page 12 Contents RM0091 16.4.7 TIM2 and TIM3 capture/compare mode register 1 (TIM2_CCMR1 and TIM3_CCMR1) ......... . . 339 16.4.8 TIM2 and TIM3 capture/compare mode register 2 (TIM2_CCMR2 and TIM3_CCMR2) .
Page 13 RM0091 Contents 17.4.4 TIM14 event generation register (TIM14_EGR) ....367 17.4.5 TIM14 capture/compare mode register 1 (TIM14_CCMR1) ..368 17.4.6 TIM14 capture/compare enable register (TIM14_CCER) .
Page 14 Contents RM0091 18.5.6 TIM15 event generation register (TIM15_EGR) ....408 18.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) ..409 18.5.8 TIM15 capture/compare enable register (TIM15_CCER) .
Page 15 RM0091 Contents Basic timer (TIM6) ......... 440 19.1 TIM6 introduction .
Page 16 Contents RM0091 21.4.6 IWDG register map ........460 System window watchdog (WWDG) .
Page 17 RM0091 Contents 23.5 C interrupts ..........517 23.6 C debug mode .
Page 18 Contents RM0091 24.5 RTC interrupts ..........549 24.6 RTC registers .
Page 19 RM0091 Contents 25.5.10 LIN (local interconnection network) mode ..... . 592 25.5.11 USART synchronous mode ....... . . 594 25.5.12 Single-wire half-duplex communication .
Page 20 Contents RM0091 26.3.8 SPI Status flags ......... . 646 26.3.9 SPI error flags .
Page 21 RM0091 Contents 27.3.4 Charge transfer acquisition sequence ......685 27.3.5 Spread spectrum feature ........686 27.3.6 Max count error .
Page 22 Contents RM0091 28.5.5 Long Bit Period Error (LBPE) ....... . 705 28.5.6 Transmission Error Detection (TXERR) .
Page 23 RM0091 Contents 29.9.2 Debug support for timers, watchdog and I C ....727 29.9.3 Debug MCU configuration register (DBGMCU_CR) ....728 29.9.4 Debug MCU APB low freeze register (DBGMCU_APB1_FZ) .
Page 24 List of tables RM0091 List of tables Table 1. Applicable products ............1 Table 2.
Page 25 RM0091 List of tables Table 48. TIM2 and TIM3 internal trigger connection ........334 Table 49.
Page 26 List of tables RM0091 Table 99. Effect of low power modes on TSC ......... 689 Table 100.
Page 27 RM0091 List of figures List of figures Figure 1. System architecture ............35 Figure 2.
Page 28 List of figures RM0091 Figure 49. Counter timing diagram, internal clock divided by N......228 Figure 50.
Page 29 RM0091 List of figures Figure 99. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)..298 Figure 100. Counter timing diagram, internal clock divided by 1 ......299 Figure 101.
Page 30 List of figures RM0091 Figure 149. Output stage of capture/compare channel (channel 1)......360 Figure 150.
Page 31 RM0091 List of figures Figure 197. I2C bus protocol ............472 Figure 198.
Page 32 List of figures RM0091 Figure 249. Hardware flow control between 2 USARTs ........606 Figure 250.
Page 33 RM0091 List of figures Figure 299. Block diagram of STM32F05xxx MCU and Cortex-M0-level debug support ..718 Doc ID 018940 Rev 1 33/742...
Page 34: Documentation Conventions
Documentation conventions RM0091 Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1.
Page 35: System And Memory Overview
RM0091 System and memory overview System and memory overview System architecture The main system consists of: ● Two masters: – Cortex-M0 core AHB bus – GP-DMA (general-purpose DMA) ● Four slaves: – Internal SRAM – Internal Flash memory – AHB to APB, which connects all the APB peripherals –...
Page 36 System and memory overview RM0091 DMA bus This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals. BusMatrix The BusMatrix manages the access arbitration between the core system bus and the DMA master bus.
Page 37: Memory Organization
RM0091 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 38 RM0091 Table 2. STM32F05xxx memory map and peripheral register boundary addresses Boundary address Size Peripheral Peripheral register map 0x4001 5C00 - 0x4001 7FFF 9 KB Reserved 0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU 0x4001 4C00 - 0x4001 57FF 3 KB Reserved 0x4001 4800 - 0x4001 4BFF 1 KB...
Page 39 RM0091 Table 2. STM32F05xxx memory map and peripheral register boundary addresses Boundary address Size Peripheral Peripheral register map 0x4000 7C00 - 0x4000 7FFF 1 KB Reserved 0x4000 7800 - 0x4000 7BFF 1 KB Section 28.7.7 on page 717 0x4000 7400 - 0x4000 77FF 1 KB Section 13.5.8 on page 214 0x4000 7000 - 0x4000 73FF...
Page 40: Embedded Sram
RM0091 Embedded SRAM The STM32F05xxx features up to 8 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). This memory can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA. Parity check The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user option byte (refer to...
Page 41 RM0091 The values on both BOOT0 pin and nBOOT1 bit are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set nBOOT1 and BOOT0 to select the required boot mode. The BOOT0 pin and nBOOT1 bit are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode.
Page 42: Embedded Flash Memory
Embedded Flash memory RM0091 Embedded Flash memory Flash main features ● Up to 64 Kbytes of Flash memory ● Memory organization: – Main Flash memory block: 16 Kwords (16K × 32 bits) – Information block: 1 Kword (1K × 32 bits) Flash memory interface features: ●...
Page 43: Read Operations
RM0091 Embedded Flash memory Table 4. Flash module organization (continued) Size Flash area Flash memory addresses Name Description (bytes) 0x1FFF EC00- 0x1FFF F7FF 3 Kbytes System memory Information block 0x1FFF F800 - 0x1FFF F80B Option bytes 0x4002 2000 - 0x4002 2003 FLASH_ACR 0x4002 2004 - 0x4002 2007 FLASH_KEYR...
Page 44: Flash Program And Erase Operations
Embedded Flash memory RM0091 no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator. Note: The prefetch buffer must be kept on (FLASH_ACR[4]=’1’) when using a prescaler different from 1 on the AHB clock.
Page 45: Figure 2. Programming Procedure
RM0091 Embedded Flash memory Unlocking the Flash memory After reset, the Flash memory is protected against unwanted write or erase operations. The FLASH_CR register is not accessible in write mode. An unlocking sequence should be written to the FLASH_KEYR register to open the access to the FLASH_CR register. This sequence consists of two write operations: ●...
Page 46 Embedded Flash memory RM0091 The Flash memory interface preliminarily reads the value at the addressed main Flash memory location and checks that it has been erased. If not, the program operation is skipped and a warning is issued by the PGERR bit in FLASH_SR register. The only exception to this is when 0x0000 is programmed.
Page 47: Figure 3. Flash Memory Page Erase Procedure
RM0091 Embedded Flash memory Figure 3. Flash memory Page Erase procedure Read LOCK bit in FLASH_CR Perform unlock sequence LOCK bit in FLASH_CR Write PER bit in FLASH_CR Write into FAR an address within the page to erase Write STRT bit in FLASH_CR to 1 BSY bit in FLASH_SR Check the page is erased by...
Page 48: Figure 4. Flash Memory Mass Erase Procedure
Embedded Flash memory RM0091 Mass Erase The Mass Erase command can be used to completely erase the user pages of the Flash memory. The information block is unaffected by this procedure. The following sequence is recommended: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register.
Page 49: Memory Protection
RM0091 Embedded Flash memory The value of the addressed option byte is first read to check it is really erased. If not, the program operation is skipped and a warning is issued by the WRPRTERR bit in the FLASH_SR register. The end of the program operation is indicated by the EOP bit in the FLASH_SR register.
Page 50: Table 5. Flash Memory Read Protection Status
Embedded Flash memory RM0091 The Flash memory is protected when the RDP option byte and its complement contain the pair of values shown in Table Table 5. Flash memory read protection status RDP byte value RDP complement value Read protection level Level 0 (ST production 0xAA 0x55...
Page 51: Write Protection
WRPRTERR is set in the Flash_SR register and an interrupt can be generated. Note: The debug feature is also disabled under reset. STMicroelectronics is not able to perform analysis on defective parts on which the level 2 protection has been set. Table 6.
Page 52: Option Byte Write Protection
Embedded Flash memory RM0091 If a program or an erase operation is performed on a protected sector, the Flash memory returns a WRPRTERR protection error flag in the Flash memory Status Register (FLASH_SR). Write unprotection To disable the write protection, two application cases are provided: ●...
Page 53: Flash Access Control Register (Flash_Acr)
RM0091 Embedded Flash memory 3.5.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRFT PRFT Res. Res. Res. Res. Res. Res.
Page 54: Flash Option Key Register (Flash_Optkeyr)
Embedded Flash memory RM0091 3.5.3 Flash option key register (FLASH_OPTKEYR) Address offset: 0x08 Reset value: xxxx xxxx All the register bits are all write-only and will return a 0 when read. OPTKEYR[31:16] OPTKEYR[15:0] Bits 31:0 OPTKEYR: Option byte key These bits represent the keys to unlock the OPTWRE. 3.5.4 Flash status register (FLASH_SR) Address offset: 0x0C...
Page 55: Flash Control Register (Flash_Cr)
RM0091 Embedded Flash memory 3.5.5 Flash control register (FLASH_CR) Address offset: 0x10 Reset value: 0x0000 0080 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FORCE_ OPTWR Res. Res. EOPIE Res. ERRIE Res. LOCK STRT OPTER...
Page 56: Flash Address Register (Flash_Ar)
Embedded Flash memory RM0091 Bit 2 MER: Mass erase Erase of all user pages chosen. Bit 1 PER: Page erase Page Erase chosen. Bit 0 PG: Programming Flash programming chosen. 3.5.6 Flash address register (FLASH_AR) Address offset: 0x14 Reset value: 0x0000 0000 This register is updated by hardware with the currently/last used address.
Page 57: Option Byte Register (Flash_Obr)
RM0091 Embedded Flash memory 3.5.7 Option byte register (FLASH_OBR) Address offset 0x1C Reset value: 0x03FF FFF2 The reset value of this register depends on the value programmed in the option byte and the OPTERR bit reset value depends on the comparison of the option byte and its complement during the option byte loading phase.
Page 58: Write Protection Register (Flash_Wrpr)
Embedded Flash memory RM0091 3.5.8 Write protection register (FLASH_WRPR) Address offset: 0x20 Reset value: 0xFFFF FFFF WRP[15:0] Bits 31:0 WRP: Write protect This register contains the write-protection option bytes loaded by the OBL. Flash register map Table 8. Flash interface - register map and reset values Offset Register FLASH_ACR...
Page 59: Option Byte Description
RM0091 Option byte description Option byte description There are six option bytes. They are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode. A 32-bit word is split up as follows in the option bytes. Table 9.
Page 60: Table 11. Description Of The Option Bytes
Option byte description RM0091 Table 11. Description of the option bytes Flash memory Option bytes address Bits [31:24] nUSER Bits [23:16] USER: User option byte (stored in FLASH_OBR[15:8]) This byte is used to configure the following features: – Select the watchdog event: Hardware or software. –...
Page 61 RM0091 Option byte description Table 11. Description of the option bytes (continued) Flash memory Option bytes address WRPx: Flash memory write protection option bytes Bits [31:24]: nWRP1 Bits [23:16]: WRP1 (stored in FLASH_WRPR[15:8]) Bits [15:8]: nWRP0 0x1FFF F808 Bits [7:0]: WRP0 (stored in FLASH_WRPR[7:0]) 0: Write protection enabled 1: Write protection disabled Refer to...
Page 62: Cyclic Redundancy Check Calculation Unit (Crc)
Cyclic redundancy check calculation unit (CRC) RM0091 Cyclic redundancy check calculation unit (CRC) Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 63: Crc Functional Description
RM0091 Cyclic redundancy check calculation unit (CRC) CRC functional description Figure 5. CRC calculation unit block diagram AHB bus 32-bit (read access) Data register (output) CRC computation 32-bit (write access) Data register (input) MS19882V1 The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access).
Page 64: Crc Registers
Cyclic redundancy check calculation unit (CRC) RM0091 The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF). The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access.
Page 65: Control Register (Crc_Cr)
RM0091 Cyclic redundancy check calculation unit (CRC) 5.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_O Res. Res. Res. Res. Res. Res.
Page 66: Initial Crc Value (Crc_Init)
Cyclic redundancy check calculation unit (CRC) RM0091 5.4.4 Initial CRC value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF CRC_INIT[31:16] CRC_INI[15:0] Bits 31:0 CRC_INIT: Programmable initial CRC value This register is used to write the CRC initial value. 5.4.5 CRC register map Table 12.
Page 67: Power Control (Pwr)
RM0091 Power control (PWR) Power control (PWR) Power supplies The device requires a 2.0 V - 3.6 V operating voltage supply (V ) and 2.0 V - 3.6 V analog voltage supply (V ). An embedded regulator is used to supply the internal 1.8 V digital power.
Page 68: Battery Backup Domain
Power control (PWR) RM0091 When V is different from V , it must always be higher or equal to V . In order to ensure this condition, also during power-up/power-down transitions, an external Shottky diode may be used between V and V 6.1.2 Battery backup domain...
Page 69: Voltage Regulator
RM0091 Power control (PWR) 6.1.3 Voltage regulator The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes. ● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals).
Page 70: Programmable Voltage Detector (Pvd)
Power control (PWR) RM0091 6.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if V...
Page 71: Low-Power Modes
RM0091 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 72: Peripheral Clock Gating
Power control (PWR) RM0091 6.3.2 Peripheral clock gating In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Page 73: Stop Mode
RM0091 Power control (PWR) Table 14. Sleep-now Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 0 Refer to the Cortex-M0 System Control register. If WFI was used for entry: Interrupt: Refer to Table 27: Vector table Mode exit...
Page 74: Standby Mode
Power control (PWR) RM0091 ● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) ● Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR). ● External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register...
Page 75: Table 17. Standby Mode
RM0091 Power control (PWR) Entering Standby mode Refer to Table 17 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: ● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option.
Page 76: Auto-Wakeup From Low-Power Mode
Power control (PWR) RM0091 Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex-M0 core is no longer clocked.
Page 77: Power Control Registers
RM0091 Power control (PWR) Power control registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 Power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) PLS[2:0] PVDE CSBF CWUF PDDS LPDS...
Page 78 Power control (PWR) RM0091 Bit 2 CWUF: Clear wakeup flag. This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write) Bit 1 PDDS: Power down deepsleep. This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters Deepsleep.
Page 79: Power Control/Status Register (Pwr_Csr)
RM0091 Power control (PWR) 6.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. EWUP EWUP PVDO Bits 31:10 Reserved, must be kept at reset value.
Page 80 Power control (PWR) RM0091 Bit 0 WUF: Wakeup flag This bit is set by hardware to indicate that the device received a wakeup event. It is cleared only by a POR/PDR (power on reset/power down reset) or by setting the CWUF bit in the Power control register (PWR_CR) 0: No wakeup event occurred 1: A wakeup event was received from one of the enabled WKUPx pins or from the RTC...
Page 81: Pwr Register Map
RM0091 Power control (PWR) 6.4.3 PWR register map The following table summarizes the PWR registers. Table 18. PWR register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reset value PWR_CSR 0x004 Reset value Refer to Section 2.2.2 on page 37 for the register boundary addresses.
Page 82: Reset And Clock Control (Rcc)
Reset and clock control (RCC) RM0091 Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and backup domain reset. 7.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 6 on page 74).
Page 83: Power Reset
RM0091 Reset and clock control (RCC) Software reset The SYSRESETREQ bit in Cortex-M0 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the Cortex™-M0 technical reference manual for more details. Low-power management reset There are two ways to generate a low-power management reset: Reset generated when entering Standby mode:...
Page 84 Reset and clock control (RCC) RM0091 The devices have the following additional clock sources: ● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode. ● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real- time clock (RTCCLK) ●...
Page 85: Figure 10. Clock Tree
RM0091 Reset and clock control (RCC) Figure 10. Clock tree FLITFCLK to Flash programming interface to I2C1 SYSCLK to I2S1 to CEC 8 MHz /256 HSI RC HCLK to AHB bus, core, memory and DMA PLLSRC to cortex System timer PLLMUL FHCLK Cortex free running clock PCLK...
Page 86: Hse Clock
Reset and clock control (RCC) RM0091 The timer clock frequencies are automatically fixed by hardware. There are two cases: if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain. otherwise, they are set to twice (×2) the frequency of the APB domain.
Page 87: Hsi Clock
RM0091 Reset and clock control (RCC) External crystal/ceramic resonator (HSE crystal) The 4 to 32 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 11. Refer to the electrical characteristics section of the datasheet for more details.
Page 88: Pll
Reset and clock control (RCC) RM0091 7.2.3 The internal PLL can be used to multiply the HSI or HSE output clock frequency. Refer to Figure 10 Clock control register (RCC_CR). The PLL configuration (selection of the input clock, and multiplication factor) must be done before enabling the PLL.
Page 89: System Clock (Sysclk) Selection
RM0091 Reset and clock control (RCC) The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).
Page 90: Rtc Clock
Reset and clock control (RCC) RM0091 7.2.9 RTC clock The RTCCLK clock source can be either the HSE/32, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The system must be always configured in a way that the PCLK frequency is greater then or equal to the RTCCLK frequency for proper operation of the RTC.
Page 91 RM0091 Reset and clock control (RCC) HDMI CEC, USART1 and I2C1 have the capability to enable the HSI oscillator even when the MCU is in Stop mode (if HSI is selected as the clock source for that peripheral). HDMI CEC and USART1 can also be driven by the LSE oscillator when the system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is enabled (LSEON) but they do not have the capability to turn on the LSE oscillator.
Page 92: Rcc Registers
Reset and clock control (RCC) RM0091 RCC registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. 7.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-?word and byte access PLLON HSICAL[7:0]...
Page 93 RM0091 Reset and clock control (RCC) Bit 17 HSERDY: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset. 0: HSE oscillator not ready 1: HSE oscillator ready Bit 16 HSEON: HSE clock enable...
Page 94: Clock Configuration Register (Rcc_Cfgr)
Reset and clock control (RCC) RM0091 7.4.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. MCO[2:0] PLLMUL[3:0] XTPRE...
Page 95 RM0091 Reset and clock control (RCC) Bits 21:18 PLLMUL: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 48 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4...
Page 96 Reset and clock control (RCC) RM0091 Bits 7:4 HPRE: HLCK prescaler Set and cleared by software to control the division factor of the AHB clock. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128...
Page 97: Clock Interrupt Register (Rcc_Cir)
RM0091 Reset and clock control (RCC) 7.4.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access HSI14 CSSC RDYC RDYC RDYC RDYC RDYC RDYC HSI14 HSI14 CSSF RDYIE RDYIE RDYIE RDYIE RDYIE...
Page 98 Reset and clock control (RCC) RM0091 Bits 15:14 Reserved, must be kept at reset value. Bit 13 HSI14RDYIE: HSI14 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI14 oscillator stabilization. 0: HSI14 ready interrupt disabled 1: HSI14 ready interrupt enabled Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock.
Page 99: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
RM0091 Reset and clock control (RCC) Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit 3 HSERDYF: HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Page 100 Reset and clock control (RCC) RM0091 Bits 22 DBGMCURST: Debug MCU reset Set and cleared by software. 0: No effect 1: Resets Debug MCU Bits 21:19 Reserved, must be kept at reset value. Bit 18 TIM17RST: TIM17 timer reset Set and cleared by software. 0: No effect 1: Reset TIM17 timer Bit 17 TIM16RST: TIM16 timer reset...
Page 101: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
RM0091 Reset and clock control (RCC) 7.4.5 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access USART I2C2 I2C1 CECR SPI2 TIM14 TIM6 TIM3 TIM2 GRST Bit 31 Reserved, must be kept at reset value. Bit 30 CECRST HDMI CEC reset Set and cleared by software.
Page 102: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
Reset and clock control (RCC) RM0091 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:9 Reserved, must be kept at reset value.
Page 103 RM0091 Reset and clock control (RCC) Bits 31:25 Reserved, must be kept at reset value. Bit 24 TSCEN: Touch sensing controller clock enable Set and cleared by software. 0: TSC clock disabled 1: TSC clock enabled Bit 23 Reserved, must be kept at reset value. Bit 22 IOPFEN: I/O port F clock enable Set and cleared by software.
Page 104: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Reset and clock control (RCC) RM0091 Bit 0 DMAEN: DMA clock enable Set and cleared by software. 0: DMA clock disabled 1: DMA clock enabled 7.4.7 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB domain is on going.
Page 105: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
RM0091 Reset and clock control (RCC) Bit 14 USART1EN: USART1clock enable Set and cleared by software. 0: USART1clock disabled 1: USART1clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 TIM1EN: TIM1 timer clock enable...
Page 106 Reset and clock control (RCC) RM0091 Bit 31 Reserved, must be kept at reset value. Bit 30 CECEN: HDMI CEC interface clock enable Set and cleared by software. 0: HDMI CEC clock disabled 1: HDMI CEC clock enabled Bit 29 DACEN: DAC interface clock enable Set and cleared by software.
Page 107 RM0091 Reset and clock control (RCC) Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM3EN: TIM3 timer clock enable Set and cleared by software.
Page 108: Backup Domain Control Register (Rcc_Bdcr)
Reset and clock control (RCC) RM0091 7.4.9 Backup domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0018, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register...
Page 109 RM0091 Reset and clock control (RCC) Bits 4:3 LSEDRV LSE oscillator drive capability Set and reset by software to modulate the LSE oscillator’s drive capability. A reset of the backup domain restores the default value. 00: ‘Xtal mode’ lower driving capability 01: ‘Xtal mode’...
Page 110: Control/Status Register (Rcc_Csr)
Reset and clock control (RCC) RM0091 7.4.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. LPWR WWDG RMVF...
Page 111 RM0091 Reset and clock control (RCC) Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 OBLRSTF: Option byte loader reset flag Set by hardware when a reset from the OBL occurs.
Page 112: Ahb Peripheral Reset Register (Rcc_Ahbrstr)
Reset and clock control (RCC) RM0091 7.4.11 AHB peripheral reset register (RCC_AHBRSTR) Address: 0x28 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access IOPF IOPD IOPC IOPB IOPA Bits 31:25 Reserved, must be kept at reset value. Bit 24 TSCRST: Touch sensing controller reset Set and cleared by software.
Page 113: Clock Configuration Register 2 (Rcc_Cfgr2)
RM0091 Reset and clock control (RCC) 7.4.12 Clock configuration register 2 (RCC_CFGR2) Address: 0x2C Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access PREDIV[3:0] Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 PREDIV[3:0] PREDIV division factor These bits are set and cleared by software to select PREDIV1 division factor.
Page 114: Clock Configuration Register 3 (Rcc_Cfgr3)
Reset and clock control (RCC) RM0091 7.4.13 Clock configuration register 3 (RCC_CFGR3) Address: 0x30 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access I2C1 USART1SW[1:0] Bits 31:9 Reserved, must be kept at reset value. Bit 8 ADCSW: ADC clock source selection This bit is set and cleared by software to select ADC clock source.
Page 115: Clock Control Register 2 (Rcc_Cr2)
RM0091 Reset and clock control (RCC) 7.4.14 Clock control register 2 (RCC_CR2) Address: 0x34 Reset value: 0x0000 XX80, where X is undefined. Access: no wait states, word, half-word and byte access HSI14 HSI14 HSI14 HSI14CAL[7:0] HSI14TRIM[4:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 HSI14CAL[7:0]: HSI14 clock calibration These bits are initialized automatically at startup.
Page 116: Rcc Register Map
Reset and clock control (RCC) RM0091 7.4.15 RCC register map The following table gives the RCC register map and the reset values. Table 19. RCC register map and reset values Offset Register RCC_CR HSICAL[7:0] HSITRIM[4:0] 0x00 Reset value PPRE RCC_CFGR MCO [2:0] PLLMUL[3:0] HPRE[3:0]...
Page 117 RM0091 Reset and clock control (RCC) Table 19. RCC register map and reset values (continued) Offset Register RCC_AHBRSTR 0x28 Reset value RCC_CFGR2 PREDIV[3:0] 0x2C Reset value RCC_CFGR3 0x30 Reset value RCC_CR2 HSI14CAL[7:0] HSI14TRIM[14:0] 0x34 Reset value X X X X X X X X Refer to Section 2.2.2 on page 37 for the register boundary addresses.
Page 118: General-Purpose I/Os (Gpio)
General-purpose I/Os (GPIO) RM0091 General-purpose I/Os (GPIO) GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 119: Figure 12. Basic Structure Of A Standard I/O Port Bit
RM0091 General-purpose I/Os (GPIO) Figure 12 Figure 13 show the basic structures of a standard and a 5 V tolerant I/O port bit, respectively. Table 21 gives the possible port bit configurations. Figure 12. Basic structure of a standard I/O port bit Analog To on-chip peripheral...
Page 120: General-Purpose I/O (Gpio)
General-purpose I/Os (GPIO) RM0091 Table 20. Port bit configuration table MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [B:A] [1:0] GP output GP output PP + PU GP output PP + PD Reserved SPEED [B:A] GP output GP output OD + PU GP output OD + PD Reserved (GP output OD)
Page 121: I/O Pin Alternate Function Multiplexer And Mapping
RM0091 General-purpose I/Os (GPIO) The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle. All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register. 8.3.2 I/O pin alternate function multiplexer and mapping The device I/O pins are connected to onboard peripherals/modules through a multiplexer...
Page 122: I/O Port Control Registers
General-purpose I/Os (GPIO) RM0091 8.3.3 I/O port control registers Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push- pull or open-drain) and speed.
Page 123: I/O Alternate Function Input/Output
RM0091 General-purpose I/Os (GPIO) The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..B)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.
Page 124: Output Configuration
General-purpose I/Os (GPIO) RM0091 Figure 14. Input floating/pull up/pull down configurations Read V DD V DD on/off TTL Schmitt protection trigger diode pull Write input driver I/O pin on/off output driver protection pull diode down V SS V SS Read/write ai15940b 8.3.10 Output configuration...
Page 125: Alternate Function Configuration
RM0091 General-purpose I/Os (GPIO) Figure 15. Output configuration Read TTL Schmitt trigger on/off protection Write diode Input driver pull I/O pin Output driver on/off P-MOS protection pull down diode Output control Read/write N-MOS Push-pull or Open-drain ai15941b 8.3.11 Alternate function configuration When the I/O port is programmed as alternate function: ●...
Page 126: Analog Configuration
General-purpose I/Os (GPIO) RM0091 8.3.12 Analog configuration When the I/O port is programmed as analog configuration: ● The output buffer is disabled ● The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). ●...
Page 127: Gpio Registers
RM0091 General-purpose I/Os (GPIO) GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The peripheral registers can be written in word, half word or byte mode. 8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..D, F) Address offset: 0x00...
Page 128: Gpio Port Output Speed Register (Gpiox_Ospeedr)
General-purpose I/Os (GPIO) RM0091 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..D, F) Address offset: 0x08 Reset value: 0x0000 0000 OSPEEDR15[1:0] OSPEEDR14[1:0] OSPEEDR13[1:0] OSPEEDR12[1:0] OSPEEDR11[1:0] OSPEEDR10[1:0] OSPEEDR9[1:0] OSPEEDR8[1:0] OSPEEDR7[1:0] OSPEEDR6[1:0] OSPEEDR5[1:0] OSPEEDR4[1:0] OSPEEDR3[1:0] OSPEEDR2[1:0] OSPEEDR1[1:0] OSPEEDR0[1:0] Bits 2y+1:2y OSPEEDRy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed.
Page 129: Gpio Port Input Data Register (Gpiox_Idr) (X = A..d, F
RM0091 General-purpose I/Os (GPIO) 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..D, F) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 130: Gpio Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A..d, F
General-purpose I/Os (GPIO) RM0091 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..D, F) Address offset: 0x18 Reset value: 0x0000 0000 BR15 BR14 BR13 BR12 BR11 BR10 BS15 BS14 BS13 BS12 BS11 BS10 Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only.
Page 131: Gpio Port Configuration Lock Register (Gpiox_Lckr) (X = A..b
RM0091 General-purpose I/Os (GPIO) 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..B) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO.
Page 132: Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A
General-purpose I/Os (GPIO) RM0091 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..B) Address offset: 0x20 Reset value: 0x0000 0000 AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0] Bits 31:0 AFRLy: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFRLy selection: 0000: AF0...
Page 133: Port Bit Reset Register (Gpiox_Brr) (X=A
RM0091 General-purpose I/Os (GPIO) 8.4.11 Port bit reset register (GPIOx_BRR) (x=A..D, F) Address offset: 0x28 Reset value: 0x0000 0000 Reserved BR15 BR14 BR13 BR12 BR11 BR10 Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only.
Page 134 General-purpose I/Os (GPIO) RM0091 Table 21. GPIO register map and reset values (continued) Offset Register GPIOx_PUPDR (where x = B..D, F) 0x0C Reset value GPIOx_IDR (where x = A..D, F) 0x10 Reset value GPIOx_ODR (where x = A..D, F) 0x14 Reset value GPIOx_BSRR (where x = A..D, F)
Page 135: System Configuration Controller (Syscfg)
RM0091 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: ● Enabling/disabling I C Fast Mode Plus on some IO ports ● Remapping some DMA trigger sources from TIM16 and TIM17, USART1, and ADC to different DMA channels ●...
Page 136: Syscfg External Interrupt Configuration Register 1
System configuration controller (SYSCFG) RM0091 Bit 12 TIM17_DMA_RMP: TIM17 DMA request remapping bit This bit is set and cleared by software. It controls the remapping of TIM17 DMA request. 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1) 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) Bit 11 TIM16_DMA_RMP: TIM16 DMA request remapping bit This bit is set and cleared by software.
Page 137 RM0091 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 0 to 3) These bits are written by software to select the source input for the EXTIx external interrupt.
Page 138: Syscfg External Interrupt Configuration Register 2
System configuration controller (SYSCFG) RM0091 9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt.
Page 139: (Syscfg_Exticr4)
RM0091 System configuration controller (SYSCFG) Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 9.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res.
Page 140: Syscfg Register Maps
System configuration controller (SYSCFG) RM0091 Bits 31:9 Reserved, must be kept at reset value Bit 8 SRAM_PEF: SRAM parity flag This bit is set by hardware when an SRAM parity error is detected. It is cleared by software by writing ‘1’. 0: No SRAM parity error detected 1: SRAM parity error detected Bits 7:3 Reserved, must be kept at reset value...
Page 141 RM0091 System configuration controller (SYSCFG) Table 22. SYSCFG register map and reset values Offset Register SYSCFG_EXTICR4 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] 0x14 Reset value SYSCFG_CFGR2 0x18 Reset value Refer to Section 2.2.2 on page 37 for the register boundary addresses. Doc ID 018940 Rev 1 141/742...
Page 142: Direct Memory Access Controller (Dma)
Direct memory access controller (DMA) RM0091 Direct memory access controller (DMA) 10.1 DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions.
Page 143: Dma Functional Description
RM0091 Direct memory access controller (DMA) The block diagram is shown in the following figure. Figure 18. DMA block diagram Flash FLITF System Cortex-M0 SRAM Ch.1 Reset & clock Ch.2 control (RCC) Bridge Ch.7 Arbiter SPI3/I2S ADC1 SPI2/I2S ADC2 AHB Slave ADC3 IWDG USART1...
Page 144: Arbiter
Direct memory access controller (DMA) RM0091 address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register ● The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register.
Page 145 RM0091 Direct memory access controller (DMA) Note: If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value.
Page 146: Programmable Data Width, Data Alignment And Endians
Direct memory access controller (DMA) RM0091 10.3.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 23: Programmable data width & endian behavior (when bits PINC = MINC = Table 23.
Page 147: Error Management
RM0091 Direct memory access controller (DMA) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: ● To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord ●...
Page 148: Figure 19. Dma Request Mapping
Direct memory access controller (DMA) RM0091 Figure 19. DMA request mapping Peripheral request signals Fixed hardware priority High priority HW request 1 Channel 1 , TIM2_CH3, TIM17_CH1, SW trigger 1 TIM17_UP (MEM2MEM bit) , SPI1_RX, USART1_TX , HW request 2 Channel 2 I2C1_TX, TIM1_CH1, SW trigger...
Page 149: Table 25. Summary Of Dma Requests For Each Channel
RM0091 Direct memory access controller (DMA) Table 25 lists the DMA requests for each channel. Table 25. Summary of DMA requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 SPI1_RX SP1_TX SPI2_RX SPI2_TX USART1_TX USART1_RX USART USART1_TX...
Page 150: Dma Registers
Direct memory access controller (DMA) RM0091 10.4 DMA registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32- bit). 10.4.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00...
Page 151: Dma Interrupt Flag Clear Register (Dma
RM0091 Direct memory access controller (DMA) 10.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTEIF5 CHTIF5 CTCIF5 CGIF5 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Bits 31:28 Reserved, must be kept at reset value.
Page 152: Dma Channel X Configuration Register (Dma_Ccrx) (X = 1
Direct memory access controller (DMA) RM0091 10.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..5, where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res.
Page 153: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
RM0091 Direct memory access controller (DMA) Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable...
Page 154: Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1
Direct memory access controller (DMA) RM0091 10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..5), where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PA[31:0]: Peripheral address...
Page 155: Dma Register Map
RM0091 Direct memory access controller (DMA) 10.4.7 DMA register map The following table gives the DMA register map and the reset values. Table 26. DMA register map and reset values Offset Register DMA_ISR 0x000 Reset value DMA_IFCR 0x004 Reset value DMA_CCR1 [1:0] 0x008...
Page 156 Direct memory access controller (DMA) RM0091 Table 26. DMA register map and reset values (continued) Offset Register DMA_CPAR4 PA[31:0] 0x04C Reset value DMA_CMAR4 MA[31:0] 0x050 Reset value 0x054 Reserved DMA_CCR5 [1:0] 0x058 Reset value DMA_CNDTR5 NDT[15:0] 0x05C Reset value DMA_CPAR5 PA[31:0] 0x060 Reset value...
Page 157: Interrupts And Events
RM0091 Interrupts and events Interrupts and events 11.1 Nested vectored interrupt controller (NVIC) 11.1.1 NVIC main features ● 32 maskable interrupt channels (not including the sixteen Cortex-M0 interrupt lines) ● 4 programmable priority levels (2 bits of interrupt priority are used) ●...
Page 158: Table 27. Vector Table
Interrupts and events RM0091 Table 27. Vector table (continued) Type of Acronym Description Address priority settable FLASH Flash global interrupt 0x0000 004C settable RCC global interrupt 0x0000 0050 settable EXTI0_1 EXTI Line[1:0] interrupts 0x0000 0054 settable EXTI2_3 EXTI Line[3:2] interrupts 0x0000 0058 settable EXTI4_15...
Page 159: Extended Interrupts And Events Controller (Exti)
RM0091 Interrupts and events 11.2 Extended interrupts and events controller (EXTI) The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to the Power Manager. The EXTI allows the management of up to 28 external/internal event line (21 external event lines and 7 internal event lines).
Page 160: Wakeup Event Management
Interrupts and events RM0091 Figure 20. EXTI external interrupt/event block diagram AMBA APB bus PCLK Peripheral interface Software Rising Falling Pending Interrupt interrupt trigger trigger request mask event selection selection register register Register regsiter regsiter To NVIC interrupt controller Edge detect Pulse Input circuit...
Page 161: Functional Description
RM0091 Interrupts and events 11.2.5 Functional description For the external interrupt lines, to generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.
Page 162: Figure 21. External Interrupt/Event Gpio Mapping
Interrupts and events RM0091 Figure 21. External interrupt/event GPIO mapping EXTI0[3:0] bits in the SYSCFG_EXTICR1 register EXTI0 EXTI1[3:0] bits in the SYSCFG_EXTICR1 register EXTI1 EXTI15[3:0] bits in the SYSCFG_EXTICR4 register PA15 PB15 EXTI15 PC15 PD15 PE15 PF15 MS19951V1 The remaining lines are connected as follow: ●...
Page 163: Exti Registers
RM0091 Interrupts and events 11.3 registers EXTI Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 11.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0F94 0000 (See note below) Res.
Page 164: Rising Trigger Selection Register (Exti_Rtsr)
Interrupts and events RM0091 11.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR19 Res. TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:20 Reserved, must be kept at reset value. Bit 19 TR19: Rising trigger event configuration bit of line 19 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line.
Page 165: Software Interrupt Event Register (Exti_Swier)
RM0091 Interrupts and events Note: The external wakeup lines are edge triggered. No glitches must be generated on these lines. If a rising edge on an external interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line.
Page 166 Interrupts and events RM0091 Bits 31:20 Reserved, must be kept at reset value. Bits 19 PR19: Pending bit on line 19 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.
Page 167: Exti Register Map
RM0091 Interrupts and events 11.3.7 EXTI register map The following table gives the EXTI register map and the reset values. Table 28. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[27:0] 0x00 Reset value EXTI_EMR MR[27:0] 0x04 Reset value EXTI_RTSR TR[17:0]...
Page 168: Analog-To-Digital Converter (Adc)
Analog-to-digital converter (ADC) RM0091 Analog-to-digital converter (ADC) 12.1 Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external and 3 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode.
Page 169: Adc Main Features
RM0091 Analog-to-digital converter (ADC) 12.2 ADC main features ● High performance – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution – ADC conversion time: 1.0 µs for 12-bit resolution (1 MHz), 0.93 µs conversion time for 10 bit resolution, faster conversion times can be obtained by lowering resolution.
Page 170: Adc Pins And Internal Signals
Analog-to-digital converter (ADC) RM0091 12.3 ADC pins and internal signals Table 29. ADC internal signals Internal signal Signal type Description name TRGx Input ADC conversion triggers Input Internal temperature sensor output voltage SENSE Input Internal voltage reference output voltage REFINT Input pin input voltage divided by 2 Table 30.
Page 171: Adc Functional Description
RM0091 Analog-to-digital converter (ADC) 12.4 ADC functional description Figure 22 shows the ADC block diagram and Table 30 gives the ADC pin description. Figure 22. ADC block diagram ≥ V Analog Supply 2.4V to 3.6 AREADY EOSMP ADC Interrupt EOSEQ SCANDIR AUTOFF up/down...
Page 172: Adc On-Off Control (Aden, Addis, Adrdy)
Analog-to-digital converter (ADC) RM0091 Software Procedure: ● Ensure that ADEN=0 ● Set ADCAL=1 ● Wait until ADCAL=0 ● The calibration factor can be read from bits 6:0 of ADC_DR register Figure 23. ADC calibration ADCAL ADC State Startup CALIBRATE CALIBRATION ADC_DR[6:0] 0x00 FACTOR...
Page 173: Adc Clock
RM0091 Analog-to-digital converter (ADC) Follow this procedure to disable the ADC: ● Check that ADSTART=0 in the ADC_CR register to ensure that no conversion is ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the the ADC_CR register and waiting until this bit is read at 0.
Page 174: Configuring The Adc
Analog-to-digital converter (ADC) RM0091 Table 31. Latency between trigger and start of conversion JITOFF_D4 JITOFF_D2 Latency between the trigger event ADC clock source and the start of conversion Dedicated 14 MHz clock Latency is not deterministic (jitter) Latency is deterministic (no jitter) PCLK divided by 2 and equal to 2.75 ADC clock cycles Latency is deterministic (no jitter)
Page 175: Programmable Sampling Time (Smp)
RM0091 Analog-to-digital converter (ADC) Temperature sensor, V and V internal channels REFINT The temperature sensor is connected to channel ADC_IN16. The internal voltage reference is connected to channel ADC1_IN17. The V channel is connected to channel REFINT ADC1_IN18. 12.4.6 Programmable sampling time (SMP) Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to be measured and the embedded sampling capacitor of the ADC.
Page 176: Continuous Conversion Mode (Cont=1)
Analog-to-digital converter (ADC) RM0091 12.4.8 Continuous conversion mode (CONT=1) In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a sequence of conversions, converting all the channels once and then automatically re-starts and continuously performs the same sequence of conversions. This mode is selected when CONT=1 in the ADC_CFGR1 register.
Page 177: Timings
RM0091 Analog-to-digital converter (ADC) 12.4.10 Timings The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: = [ 1.5 + 12.5 ] x t SMPL...
Page 178: Conversion On External Trigger And Trigger Polarity (Extsel, Exten)
Analog-to-digital converter (ADC) RM0091 Figure 26. Stopping an ongoing conversion ADC State SAMPLING CH(N) CONVERTING CH(N) cleared by SW by HW ADSTART cleared by HW by SW ADSTOP DATA N-1 ADC_DR 12.5 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) A conversion or a sequence of conversion can be triggered either by software or by an external event (for example timer capture).
Page 179: Discontinuous Mode (Discen)
RM0091 Analog-to-digital converter (ADC) Table 33. External triggers (continued) Name Source EXTSEL[2:0] TRG2 TIM2_TRGO TRG3 TIM3_TRGO TRG4 TIM15_TRGO TRG5 Reserved TRG6 Reserved TRG7 Reserved Note: The trigger selection can not be changed on the fly. 12.5.1 Discontinuous mode (DISCEN) This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register. In this mode (DISCEN=1), a hardware or software trigger event is required to start each conversion defined in the sequence.
Page 180: End Of Conversion, End Of Sampling Phase (Eoc, Eosmp Flags)
Analog-to-digital converter (ADC) RM0091 Lower resolution reduces the conversion time needed for the successive approximation steps as shown in Table Table 34. timings depending on resolution SMPL (min) RES[1:0] (ns) at (µs) at (ADC clock cycles) (ADC clock (ADC clock bits = 14 MHz = 14 MHz...
Page 181: Example Timing Diagrams
RM0091 Analog-to-digital converter (ADC) 12.5.5 Example timing diagrams (single/continuous modes hardware/software triggers) Figure 27. Single conversions of a sequence, software trigger ADSTART(1) EOSEQ SCANDIR CH10 CH17 CH17 CH10 ADC state ADC_DR by S/W by H/W 1. EXTEN=0x0, CONT=0 2. CHSEL=0x20601, AUTDLY=0, AUTOFF=0 Figure 28.
Page 182: Figure 29. Single Conversions Of A Sequence, Hardware Trigger
Analog-to-digital converter (ADC) RM0091 Figure 29. Single conversions of a sequence, hardware trigger ADSTART EOSEQ TRGx ADC state ADC_DR by S/W by H/W triggered ignored 1. EXTSEL=TRGx (over-frequencied), EXTEN=0x1 (rising edge), CONT=0 2. CHSEL=0xF, SCANDIR=0, AUTDLY=0, AUTOFF=0 Figure 30. Continuous conversions of a sequence, hardware trigger ADSTART EOSEQ ADSTP...
Page 183: Data Management
RM0091 Analog-to-digital converter (ADC) 12.6 Data management 12.6.1 Data register & data alignment (ADC_DR, ALIGN) At the end of each conversion (when an EOC event occurs), the result of the converted data is stored in the ADC_DR data register which is 16-bit wide. The format of the ADC_DR depends on the configured data alignment and resolution.
Page 184: Managing A Sequence Of Data Converted Without Using The Dma
Analog-to-digital converter (ADC) RM0091 Figure 32. Example of overrun (OVR) ADSTART EOSEQ ADSTP TRGx ADC state CH0 STOP ADC_DR Read Access OVERRUN ADC_DR (OVRMOD=0) ADC_DR (OVRMOD=1) by S/W by H/W triggered 12.6.3 Managing a sequence of data converted without using the DMA If the conversions are slow enough, the conversion sequence can be handled by software.
Page 185: Low Power Features
RM0091 Analog-to-digital converter (ADC) converted data from the ADC_DR register to the destination location selected by the software. Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA.
Page 186: Auto-Off Mode (Autoff)
Analog-to-digital converter (ADC) RM0091 When the WAIT bit is set to 1 in the ADC_CFGR1 register, a new conversion can start only if the previous data has been treated, once the ADC_DR register has been read or if the EOC bit has been cleared. This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data.
Page 187: Analog Window Watchdog
RM0091 Analog-to-digital converter (ADC) Note: Please refer to the Section 7: Reset and clock control (RCC) on page 82 for the description of how to manage the dedicated 14 MHz internal oscillator. The ADC interface can automatically switch ON/OFF the 14 MHz internal oscillator to save power. Figure 34.
Page 188: Table 35. Analog Watchdog Comparison
Analog-to-digital converter (ADC) RM0091 The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by setting the AWDIE bit in the ADC_IER register.
Page 189: Temperature Sensor And Internal Reference Voltage
RM0091 Analog-to-digital converter (ADC) 12.9 Temperature sensor and internal reference voltage The temperature sensor can be used to measure the junction temperature (T ) of the device. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor’s output voltage to a digital value. The sampling time for the temperature sensor’s analog pin must be greater than 2.2 µs.
Page 190: Battery Voltage Monitoring
Analog-to-digital converter (ADC) RM0091 Reading the temperature To use the sensor: Select the ADC1_IN16 input channel Select a sampling time of 17.1 µs Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from power down mode Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by external trigger) Read the resulting V...
Page 191: Adc Interrupts
RM0091 Analog-to-digital converter (ADC) 12.11 ADC interrupts An interrupt can be generated by any of the following events: ● ADC power-up, when the ADC is ready (ADRDY flag) ● End of any conversion (EOC flag) ● End of a sequence of conversions (EOSEQ flag) ●...
Page 192: Adc Registers
Analog-to-digital converter (ADC) RM0091 12.12 ADC registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. 12.12.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res.
Page 193: Adc Interrupt Enable Register (Adc_Ier)
RM0091 Analog-to-digital converter (ADC) Bit 0 ADRDY: ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 1: ADC is ready to start conversion...
Page 194: Adc Control Register (Adc_Cr)
Analog-to-digital converter (ADC) RM0091 Bit 2 EOCIE: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. 0: EOC interrupt disabled 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
Page 195 RM0091 Analog-to-digital converter (ADC) Bit 4 ADSTP: ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command.
Page 196: Adc Configuration Register 1 (Adc_Cfgr1)
Analog-to-digital converter (ADC) RM0091 12.12.4 ADC configuration register 1 (ADC_CFGR1) Address offset: 0x0C Reset value: 0x0000 0000 DISC Res. AWDCH[4:0] Res. Res. Res. Res. Res. Res. Res. SCAN CONT EXTEN[1:0] Res. EXTSEL[2:0] ALIGN RES[1:0] Bit 31 Reserved, must be kept at reset value. Bits 30:26 AWDCH[4:0]: Analog watchdog channel selection These bits are set and cleared by software.
Page 197 RM0091 Analog-to-digital converter (ADC) Bit 16 DISCEN: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. 0: Discontinuous mode disabled 1: Discontinuous mode enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1.
Page 198 Analog-to-digital converter (ADC) RM0091 Bits 8:6 EXTSEL[2:0]: External trigger selection These bits select the external event used to trigger the start of conversion: 000: TRG0 001: TRG1 010: TRG2 011: TRG3 100: TRG4 101: TRG5 110: TRG6 111: TRG7 Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).
Page 199: Adc Configuration Register 2 (Adc_Cfgr2)
RM0091 Analog-to-digital converter (ADC) Bit 0 DMAEN: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA controller to manage automatically the converted data. For more details, refer to Section 12.6.5: Managing converted data using the DMA on page 184.
Page 200: Adc Sampling Time Register (Adc_Smpr)
Analog-to-digital converter (ADC) RM0091 12.12.6 ADC sampling time register (ADC_SMPR) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 201: Adc Channel Selection Register (Adc_Chselr)
RM0091 Analog-to-digital converter (ADC) Bit 11:0 LT[11:0]: Analog watchdog lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section 12.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD) on page 187 Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).
Page 202: Adc Common Configuration Register (Adc_Ccr)
Analog-to-digital converter (ADC) RM0091 Bits 15:0 DATA[15:0]: Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure 31: Data alignment and resolution on page 183.
Page 203: 12.12.11 Adc Register Map
RM0091 Analog-to-digital converter (ADC) 12.12.11 ADC register map The following table summarizes the ADC registers. Table 38. ADC register map and reset values Offset Register ADC_ISR 0x00 Reset value ADC_IER 0x04 Reset value ADC_CR 0x08 Reset value EXTSEL ADC_CFGR1 AWDCH[4:0] 0x0C [2:0] [1:0]...
Page 204 Analog-to-digital converter (ADC) RM0091 Table 38. ADC register map and reset values (continued) Offset Register 0x44 Reserved Reserved 0x2FC ADC_CCR 0x308 Reset value Refer to Section 2.2.2 on page 37 for the register boundary addresses. 204/742 Doc ID 018940 Rev 1...
Page 205: Digital-To-Analog Converter (Dac1)
RM0091 Digital-to-analog converter (DAC1) Digital-to-analog converter (DAC1) 13.1 DAC1 introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.An input reference voltage, V (shared with ADC) is available.
Page 206: Single Mode Functional Description
Digital-to-analog converter (DAC1) RM0091 Figure 38. DAC1 block diagram DAC control register TSELx[2:0] bits SWTRIGx TIM6_TRGO DMAENx TIM3_TRGO TIM15_TRGO TIM2_TRGO EXTI_9 DM A req ue stx TENx 12-bit DHRx Control logic BOFF 12-bit DORx 12-bit Digital-to-analog DAC1_ OU T converterx MS19883V3 Table 39.
Page 207: Dac Output Buffer Enable
RM0091 Digital-to-analog converter (DAC1) Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset. 13.3.2 DAC output buffer enable The DAC integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier.
Page 208: Dac Output Voltage
Digital-to-analog converter (DAC1) RM0091 Figure 40. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage 0x1AC available on DAC_OUT pin SETTLING ai14711b 13.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and VDDA. The analog output voltages on each DAC channel pin are determined by the following equation: ×...
Page 209: Dma Request
RM0091 Digital-to-analog converter (DAC1) Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle. 13.4 DMA request Each DAC channel has a DMA capability.
Page 210 Digital-to-analog converter (DAC1) RM0091 Bits 31:14 Reserved, must be kept at reset value. Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 0: DAC channel1 DMA Underrun Interrupt disabled 1: DAC channel1 DMA Underrun Interrupt enabled Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software.
Page 211: Dac Software Trigger Register (Dac_Swtrigr)
RM0091 Digital-to-analog converter (DAC1) 13.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 212: Dac Channel1 8-Bit Right Aligned Data Holding Register
Digital-to-analog converter (DAC1) RM0091 Bits 31:16 Reserved, must be kept at reset value. Bit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. 13.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
Page 213: Dac Status Register (Dac_Sr)
RM0091 Digital-to-analog converter (DAC1) 13.5.7 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAUDR1 Res. Res. Res. Res. Res. Res.
Page 214: Dac Register Map
Digital-to-analog converter (DAC1) RM0091 13.5.8 DAC register map Table 41 summarizes the DAC registers. Table 41. DAC register map and reset values. Address Register offset name DAC_CR 0x00 Reset value DAC_ SWTRIGR 0x04 Reset value DAC_DHR1 DACC1DHR[11:0] 0x08 Reset value DAC_DHR1 DACC1DHR[11:0] 0x0C...
Page 215: Comparator (Comp)
RM0091 Comparator (COMP) Comparator (COMP) 14.1 COMP introduction The STM32F05xxx embeds two general purpose comparators COMP1 and COMP2 that can be used either as standalone devices (all terminal are available on I/Os) or combined with the timers. They can be used for a variety of functions including: ●...
Page 216: Comp Functional Description
Comparator (COMP) RM0091 14.3 COMP functional description 14.3.1 General description The block diagram of the comparators is shown in Figure 41: Comparators block diagram. Figure 41. Comparators block diagram COMP1_OUT PA0 /PA6 /PA11 COMP1_INP COMP interrupt request COMP1 (to EXTI) COMP1_INM TIM1_BK1 Polarity...
Page 217: Interrupt And Wakeup
RM0091 Comparator (COMP) The output can also be internally redirected to a variety of timer input for the following purposes: ● Emergency shut-down of PWM signals, using BKIN ● Cycle-by-cycle current control, using OCref_clr inputs ● Input capture for timing measures It is possible to have the comparator output simultaneously redirected internally and externally.
Page 218: Figure 42. Comparator Hysteresis
Comparator (COMP) RM0091 Figure 42. Comparator hysteresis INM - V hys t COMP_OUT MS19984V1 218/742 Doc ID 018940 Rev 1...
Page 219: Comp Registers
RM0091 Comparator (COMP) 14.4 COMP registers 14.4.1 COMP control and status register (COMP_CSR) Address offset : 0x1C Reset value: 0x0000 0000 COMP COMP COMP2HYST COMP WNDW COMP2MODE COMP2 COMP2OUTSEL[2:0] COMP2INSEL[2:0] Res. 2LOCK 2OUT [1:0] 2POL [1:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r...
Page 220 Comparator (COMP) RM0091 Bit 23 WNDWEN: Window mode enable This bit connects the non-inverting input of COMP2 to COMP1’s non-inverting input, which is simultaneously disconnected from PA3. 0 : Window mode disabled 1 : Window mode enabled Bits 22:20 COMP2INSEL[2:0]: Comparator 2 inverting input selection These bits allows to select the source connected to the inverting input of the comparator 2.
Page 221 RM0091 Comparator (COMP) Bits 10:8 COMP1OUTSEL[2:0]: Comparator 1 output selection These bits selects the destination of the comparator 1 output. 000: no selection 001: Timer 1 break input 010: Timer 1 Input capture 1 011: Timer 1 OCrefclear input 100: Timer 2 input capture 4 101: Timer 2 OCrefclear input 110: Timer 3 input capture 1 111: Timer 3 OCrefclear input...
Page 222: Comp Register Map
Comparator (COMP) RM0091 14.4.2 COMP register map The following table summarizes the comparator registers Table 42. COMP register map and reset values Offset Register COMP_CSR 0x1C Reset value Refer to Section 2.2.2 on page 37 for the register boundary addresses. 222/742 Doc ID 018940 Rev 1...
Page 223: Advanced-Control Timers (Tim1)
RM0091 Advanced-control timers (TIM1) Advanced-control timers (TIM1) 15.1 TIM1 introduction The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 224: Figure 43. Advanced-Control Timer Block Diagram
Advanced-control timers (TIM1) RM0091 Figure 43. Advanced-control timer block diagram Internal Clock (CK_INT) CK_TIM18 from RCC ETRF Trigger ETRP Controller Polarity Selection & Edge TRGO TIMx_ETR Input Filter Detector & Prescaler to other timers ITR0 to DAC/ADC ITR1 Slave Reset, Enable, Up/Down, Count ITR2 Mode TRGI...
Page 225: Tim1 Functional Description
RM0091 Advanced-control timers (TIM1) 15.3 TIM1 functional description 15.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 226: Figure 44. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Advanced-control timers (TIM1) RM0091 Figure 44. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 45.
Page 227: Counter Modes
RM0091 Advanced-control timers (TIM1) 15.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR).
Page 228: Figure 47. Counter Timing Diagram, Internal Clock Divided By 2
Advanced-control timers (TIM1) RM0091 Figure 47. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 48. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT...
Page 229: Figure 50. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
RM0091 Advanced-control timers (TIM1) Figure 50. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register Write a new value in TIMx_ARR...
Page 230: Figure 52. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1) RM0091 The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).
Page 231: Figure 54. Counter Timing Diagram, Internal Clock Divided By 4
RM0091 Advanced-control timers (TIM1) Figure 54. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0001 0000 0036 0035 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 55. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 232 Advanced-control timers (TIM1) RM0091 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.
Page 233: Figure 57. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
RM0091 Advanced-control timers (TIM1) Figure 57. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 03 02 01 00 01 03 04 05 06 05 04 03 Counter underflow Counter overflow Update event (UEV) Update interrupt flag (UIF) Section 15.4: TIM1 registers on page...
Page 234: Figure 60. Counter Timing Diagram, Internal Clock Divided By N
Advanced-control timers (TIM1) RM0091 Figure 60. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 61. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timer clock = CK_CNT Counter register...
Page 235: Repetition Counter
RM0091 Advanced-control timers (TIM1) Figure 62. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register F8 F9 FA FB FC 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 236: Figure 63. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timers (TIM1) RM0091 Figure 63. Update rate examples depending on mode and TIMx_RCR register settings Center-aligned mode Edge-aligned mode Upcounting Downcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR re-synchronization (by SW) (by SW) (by SW) Update Event: Preload registers transferred to active registers and update interrupt generated...
Page 237: Clock Sources
RM0091 Advanced-control timers (TIM1) 15.3.4 Clock sources The counter clock can be provided by the following clock sources: ● Internal clock (CK_INT) ● External clock mode1: external input pin ● External clock mode2: external trigger input ETR ● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2.
Page 238: Figure 66. Control Circuit In External Clock Mode 1
Advanced-control timers (TIM1) RM0091 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 239: Capture/Compare Channels
RM0091 Advanced-control timers (TIM1) For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 240: Figure 69. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced-control timers (TIM1) RM0091 Figure 69. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1F_Rising TI1F TI1FP1 filter Edge downcounter Detector TI1F_Falling TI2FP1 IC1PS divider /1, /2, /4, /8 ICF[3:0] CC1P/CC1NP TIMx_CCER (from slave mode TIMx_CCMR1 controller) TI2F_rising...
Page 241: Figure 71. Output Stage Of Capture/Compare Channel (Channel 1 To 3)
RM0091 Advanced-control timers (TIM1) Figure 71. Output stage of capture/compare channel (channel 1 to 3) Output enable ‘0’ circuit OC1_DT CC1P CNT>CCR1 OC1REF Output mode Dead-time TIM1_CCER CNT=CCR1 controller generator OC1N_DT OC1N Output ‘0’ enable circuit CC1NE CC1E TIM1_CCER OC1CE OC1M[2:0] DTG[7:0] CC1NE...
Page 242: Input Capture Mode
Advanced-control timers (TIM1) RM0091 15.3.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 243: Pwm Input Mode
RM0091 Advanced-control timers (TIM1) 15.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: ● Two ICx signals are mapped on the same TIx input. ● These 2 ICx signals are active on edges with opposite polarity. ●...
Page 244: Forced Output Mode
Advanced-control timers (TIM1) RM0091 15.3.8 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 245: Pwm Mode
RM0091 Advanced-control timers (TIM1) Procedure: Select the counter clock (internal, external, prescaler). Write the desired data in the TIMx_ARR and TIMx_CCRx registers. Set the CCxIE bit if an interrupt request is to be generated. Select the output mode. For example: –...
Page 246: Figure 75. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1) RM0091 OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details.
Page 247: Figure 76. Center-Aligned Pwm Waveforms (Arr=8)
RM0091 Advanced-control timers (TIM1) PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration.
Page 248: Complementary Outputs And Dead-Time Insertion
Advanced-control timers (TIM1) RM0091 Hints on using center-aligned mode: ● When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Page 249: Figure 77. Complementary Output With Dead-Time Insertion
RM0091 Advanced-control timers (TIM1) Figure 77. Complementary output with dead-time insertion. OCxREF delay OCxN delay Figure 78. Dead-time waveforms with delay greater than the negative pulse. OCxREF delay OCxN Figure 79. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay...
Page 250: Using The Break Function
Advanced-control timers (TIM1) RM0091 15.3.12 Using the break function When using the break function, the output enable signals and inactive levels are modified according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs cannot be set both to active level at a given time.
Page 251 RM0091 Advanced-control timers (TIM1) Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared. The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register.
Page 252: Figure 80. Output Behavior In Response To A Break
Advanced-control timers (TIM1) RM0091 Figure 80. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 253: Clearing The Ocxref Signal On An External Event
RM0091 Advanced-control timers (TIM1) 15.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 254: 6-Step Pwm Generation
Advanced-control timers (TIM1) RM0091 15.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 255: One-Pulse Mode
RM0091 Advanced-control timers (TIM1) 15.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 256: Encoder Interface Mode
Advanced-control timers (TIM1) RM0091 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ● The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 257: Table 43. Counting Direction Versus Encoder Signals
RM0091 Advanced-control timers (TIM1) Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting.
Page 258: Figure 84. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timers (TIM1) RM0091 Figure 84. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down Figure 85 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 85.
Page 259: Timer Input Xor Function
RM0091 Advanced-control timers (TIM1) 15.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 260: Figure 86. Example Of Hall Sensor Interface
Advanced-control timers (TIM1) RM0091 Figure 86 describes this example. Figure 86. Example of hall sensor interface TIH1 TIH2 TIH3 counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step ai17336 260/742 Doc ID 018940 Rev 1...
Page 261: Timx And External Trigger Synchronization
RM0091 Advanced-control timers (TIM1) 15.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 262: Figure 88. Control Circuit In Gated Mode
Advanced-control timers (TIM1) RM0091 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 263: Figure 89. Control Circuit In Trigger Mode
RM0091 Advanced-control timers (TIM1) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 264: Timer Synchronization
Advanced-control timers (TIM1) RM0091 Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source –...
Page 265: Tim1 Registers
RM0091 Advanced-control timers (TIM1) 15.4 TIM1 registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. 15.4.1 TIM1 control register 1 (TIM1_CR1) Address offset: 0x00 Reset value: 0x0000 Res. Res. Res. Res. Res. Res.
Page 266: Tim1 Control Register 2 (Tim1_Cr2)
Advanced-control timers (TIM1) RM0091 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 267 RM0091 Advanced-control timers (TIM1) Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 268: Tim1 Slave Mode Control Register (Tim1_Smcr)
Advanced-control timers (TIM1) RM0091 Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 269 RM0091 Advanced-control timers (TIM1) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 270: Tim1 Dma/Interrupt Enable Register (Tim1_Dier)
Advanced-control timers (TIM1) RM0091 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 271 RM0091 Advanced-control timers (TIM1) Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled...
Page 272: Tim1 Status Register (Tim1_Sr)
Advanced-control timers (TIM1) RM0091 15.4.5 TIM1 status register (TIM1_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value.
Page 273: Tim1 Event Generation Register (Tim1_Egr)
RM0091 Advanced-control timers (TIM1) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 274 Advanced-control timers (TIM1) RM0091 Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
Page 275: Tim1 Capture/Compare Mode Register 1 (Tim1_Ccmr1)
RM0091 Advanced-control timers (TIM1) 15.4.7 TIM1 capture/compare mode register 1 (TIM1_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 276 Advanced-control timers (TIM1) RM0091 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 277 RM0091 Advanced-control timers (TIM1) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 278: Tim1 Capture/Compare Mode Register 2 (Tim1_Ccmr2)
Advanced-control timers (TIM1) RM0091 Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 279: Tim1 Capture/Compare Enable Register (Tim1_Ccer)
RM0091 Advanced-control timers (TIM1) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 280 Advanced-control timers (TIM1) RM0091 Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configuration as output:...
Page 281 RM0091 Advanced-control timers (TIM1) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
Page 282: Table 45. Output Control Bits For Complementary Ocx And Ocxn Channels With
Advanced-control timers (TIM1) RM0091 Table 45. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the the timer) timer) OCx=0, OCx_EN=0...
Page 283: Tim1 Counter (Tim1_Cnt)
RM0091 Advanced-control timers (TIM1) 1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared. Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers.
Page 284: Tim1 Repetition Counter Register (Tim1_Rcr)
Advanced-control timers (TIM1) RM0091 15.4.13 TIM1 repetition counter register (TIM1_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 285: Tim1 Capture/Compare Register 2 (Tim1_Ccr2)
RM0091 Advanced-control timers (TIM1) 15.4.15 TIM1 capture/compare register 2 (TIM1_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 286: Tim1 Capture/Compare Register 4 (Tim1_Ccr4)
Advanced-control timers (TIM1) RM0091 15.4.17 TIM1 capture/compare register 4 (TIM1_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 287 RM0091 Advanced-control timers (TIM1) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 288: Tim1 Dma Control Register (Tim1_Dcr)
Advanced-control timers (TIM1) RM0091 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 289: Tim1 Dma Address For Full Transfer (Tim1_Dmar)
RM0091 Advanced-control timers (TIM1) 15.4.20 TIM1 DMA address for full transfer (TIM1_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 290: Tim1 Register Map
Advanced-control timers (TIM1) RM0091 15.4.21 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 46. TIM1 register map and reset values Offset Register TIM1_CR1 [1:0] [1:0] 0x00 Reset value TIM1_CR2 MMS[2:0] 0x04 Reset value ETPS...
Page 291 RM0091 Advanced-control timers (TIM1) Table 46. TIM1 register map and reset values (continued) Offset Register TIM1_CCR1 CCR1[15:0] 0x34 Reset value TIM1_CCR2 CCR2[15:0] 0x38 Reset value TIM1_CCR3 CCR3[15:0] 0x3C Reset value TIM1_CCR4 CCR4[15:0] 0x40 Reset value LOCK TIM1_BDTR DT[7:0] [1:0] 0x44 Reset value TIM1_DCR DBL[4:0]...
Page 292: General-Purpose Timers (Tim2 And Tim3)
General-purpose timers (TIM2 and TIM3) RM0091 General-purpose timers (TIM2 and TIM3) 16.1 TIM2 and TIM3 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 293: Tim2 And Tim3 Functional Description
RM0091 General-purpose timers (TIM2 and TIM3) Figure 91. General-purpose timer block diagram (TIM2 and TIM3) Internal Clock (CK_INT) TIMxCLK from RCC ETRF ETRP Polarity selection & edge TIMx_ETR Input filter detector & prescaler TRGO ITR0 Trigger to other timers controller ITR1 to DAC/ADC ITR2...
Page 294: Figure 92. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2 and TIM3) RM0091 The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 295: Counter Modes
RM0091 General-purpose timers (TIM2 and TIM3) Figure 93. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter 16.3.2...
Page 296: Figure 94. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 and TIM3) RM0091 Figure 94. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 95.
Page 297: Figure 97. Counter Timing Diagram, Internal Clock Divided By N
RM0091 General-purpose timers (TIM2 and TIM3) Figure 97. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 98. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN...
Page 298: Figure 99. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2 and TIM3) RM0091 Figure 99. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 299: Figure 100. Counter Timing Diagram, Internal Clock Divided By 1
RM0091 General-purpose timers (TIM2 and TIM3) Figure 100. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 101.
Page 300: Figure 103. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 and TIM3) RM0091 Figure 103. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 104. Counter timing diagram, Update event when repetition counter is not used CK_INT CNT_EN...
Page 301: Figure 105. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0091 General-purpose timers (TIM2 and TIM3) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
Page 302: Figure 106. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2 and TIM3) RM0091 Figure 106. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN TImer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 107.
Page 303: Figure 109. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
RM0091 General-purpose timers (TIM2 and TIM3) Figure 109. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register 05 04 03 02 01 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR...
Page 304: Clock Sources
General-purpose timers (TIM2 and TIM3) RM0091 16.3.3 Clock sources The counter clock can be provided by the following clock sources: ● Internal clock (CK_INT) ● External clock mode1: external input pin (TIx) ● External clock mode2: external trigger input (ETR) ●...
Page 305: Figure 112. Ti2 External Clock Connection Example
RM0091 General-purpose timers (TIM2 and TIM3) Figure 112. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F encoder ITRx mode TI1F_ED external clock TRGI TI1FP1 mode 1 CK_PSC TI2F_Rising TI2FP2 Edge Filter Detector TI2F_Falling ETRF external clock ETRF mode 2 CK_INT ICF[3:0] CC2P...
Page 306: Figure 114. External Trigger Input Block
General-purpose timers (TIM2 and TIM3) RM0091 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 114 gives an overview of the external trigger input block.
Page 307: Capture/Compare Channels
RM0091 General-purpose timers (TIM2 and TIM3) 16.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). The following figure gives an overview of one Capture/Compare channel.
Page 308: Input Capture Mode
General-purpose timers (TIM2 and TIM3) RM0091 Figure 118. Output stage of capture/compare channel (channel 1) OCREF_CLR ocref_clr_int ETRF To the master mode controller Output OCCS Enable Circuit TIMx_SMCR CC1P CNT > CCR1 oc1ref Output mode TIMx_CCER CNT = CCR1 controller CC1E TIMx_CCER OC1M[2:0]...
Page 309 RM0091 General-purpose timers (TIM2 and TIM3) detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. ● Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case). ●...
Page 310: Pwm Input Mode
General-purpose timers (TIM2 and TIM3) RM0091 16.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: ● Two ICx signals are mapped on the same TIx input. ● These 2 ICx signals are active on edges with opposite polarity. ●...
Page 311: Forced Output Mode
RM0091 General-purpose timers (TIM2 and TIM3) 16.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
Page 312: Pwm Mode
General-purpose timers (TIM2 and TIM3) RM0091 The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 120.
Page 313: Figure 121. Edge-Aligned Pwm Waveforms (Arr=8)
RM0091 General-purpose timers (TIM2 and TIM3) This forces the PWM by software while the timer is running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low.
Page 314: Figure 122. Center-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 and TIM3) RM0091 Figure 122 shows some center-aligned PWM waveforms in an example where: ● TIMx_ARR=8, ● PWM mode is the PWM mode 1, ● The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
Page 315: One-Pulse Mode
RM0091 General-purpose timers (TIM2 and TIM3) Hints on using center-aligned mode: ● When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register.
Page 316: Clearing The Ocxref Signal On An External Event
General-purpose timers (TIM2 and TIM3) RM0091 Use TI2FP2 as trigger 1: ● Map TI2FP2 on TI2 by writing IC2S=01 in the TIMx_CCMR1 register. ● TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. ● Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
Page 317: Encoder Interface Mode
RM0091 General-purpose timers (TIM2 and TIM3) Figure 124 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode. Figure 124.
Page 318: Table 47. Counting Direction Versus Encoder Signals
General-purpose timers (TIM2 and TIM3) RM0091 Table 47. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count...
Page 319: Timer Input Xor Function
RM0091 General-purpose timers (TIM2 and TIM3) Figure 126 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 126. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward Counter down...
Page 320: Timers And External Trigger Synchronization
General-purpose timers (TIM2 and TIM3) RM0091 16.3.14 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 321: Figure 128. Control Circuit In Gated Mode
RM0091 General-purpose timers (TIM2 and TIM3) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 322: Figure 129. Control Circuit In Trigger Mode
General-purpose timers (TIM2 and TIM3) RM0091 When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
Page 323: Timer Synchronization
RM0091 General-purpose timers (TIM2 and TIM3) Figure 130. Control circuit in external clock mode 2 + trigger mode CEN/CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 16.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Page 324: Figure 132. Gating Timer 2 With Oc1Ref Of Timer 1
General-purpose timers (TIM2 and TIM3) RM0091 Using one timer to enable another timer In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1. Refer to Figure 131 for connections. Timer 2 counts on the divided internal clock only when OC1REF of Timer 1 is high.
Page 325: Figure 133. Gating Timer 2 With Enable Of Timer 1
RM0091 General-purpose timers (TIM2 and TIM3) In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers.
Page 326: Figure 134. Triggering Timer 2 With Update Of Timer 1
General-purpose timers (TIM2 and TIM3) RM0091 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 131 for connections. Timer 2 starts counting from its current value (which can be nonzero) on the divided internal clock as soon as the update event is generated by Timer 1.
Page 327: Figure 135. Triggering Timer 2 With Enable Of Timer 1
RM0091 General-purpose timers (TIM2 and TIM3) Figure 135. Triggering timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF Write TIF=0 Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 131 for connections.
Page 328: Debug Mode
General-purpose timers (TIM2 and TIM3) RM0091 When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal clock and both TIF flags are set. Note: In this example both timers are initialized before starting (by setting their respective UG bits).
Page 329: Tim2 And Tim3 Registers
RM0091 General-purpose timers (TIM2 and TIM3) 16.4 TIM2 and TIM3 registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 16.4.1 TIM2 and TIM3 control register 1 (TIM2_CR1 and TIM3_CR1) Address offset: 0x00 Reset value: 0x0000...
Page 330 General-purpose timers (TIM2 and TIM3) RM0091 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 331: Tim2 And Tim3 Control Register 2 (Tim2_Cr2 And Tim3_Cr2)
RM0091 General-purpose timers (TIM2 and TIM3) 16.4.2 TIM2 and TIM3 control register 2 (TIM2_CR2 and TIM3_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Page 332: Tim2 And Tim3 Slave Mode Control Register
General-purpose timers (TIM2 and TIM3) RM0091 16.4.3 TIM2 and TIM3 slave mode control register (TIM2_SMCR and TIM3_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 333 RM0091 General-purpose timers (TIM2 and TIM3) Bits 11:8 ETF[3:0]: External trigger filter This bit-field defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 334: Table 48. Tim2 And Tim3 Internal Trigger Connection
General-purpose timers (TIM2 and TIM3) RM0091 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 335: Tim2 And Tim3 Dma/Interrupt Enable Register
RM0091 General-purpose timers (TIM2 and TIM3) 16.4.4 TIM2 and TIM3 DMA/Interrupt enable register (TIM2_DIER and TIM3_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4DE CC3DE CC2DE CC1DE Res. Res. CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 336: Tim2 And Tim3 Status Register (Tim2_Sr And Tim3_Sr)
General-purpose timers (TIM2 and TIM3) RM0091 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 16.4.5...
Page 337 RM0091 General-purpose timers (TIM2 and TIM3) Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 338: Tim2 And Tim3 Event Generation Register (Tim2_Egr And Tim3_Egr)
General-purpose timers (TIM2 and TIM3) RM0091 16.4.6 TIM2 and TIM3 event generation register (TIM2_EGR and TIM3_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC4G CC3G CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 339: Tim2 And Tim3 Capture/Compare Mode Register
RM0091 General-purpose timers (TIM2 and TIM3) 16.4.7 TIM2 and TIM3 capture/compare mode register 1 (TIM2_CCMR1 and TIM3_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 340 General-purpose timers (TIM2 and TIM3) RM0091 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 341 RM0091 General-purpose timers (TIM2 and TIM3) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 342: Tim2 And Tim3 Capture/Compare Mode Register
General-purpose timers (TIM2 and TIM3) RM0091 16.4.8 TIM2 and TIM3 capture/compare mode register 2 (TIM2_CCMR2 and TIM3_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0]...
Page 343: Tim2 And Tim3 Capture/Compare Enable Register
RM0091 General-purpose timers (TIM2 and TIM3) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 344: Table 49. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM2 and TIM3) RM0091 Bit 8 CC3E: Capture/Compare 3 output enable. Refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 output Polarity. Refer to CC1NP description Bit 6 Reserved, always read as 0. Bit 5 CC2P: Capture/Compare 2 output Polarity. Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable.
Page 345: Tim2 And Tim3 Counter (Tim2_Cnt And Tim3_Cnt)
RM0091 General-purpose timers (TIM2 and TIM3) Note: The state of the external IO pins connected to the standard OCx channels depends on the OCx channel state and the GPIO registers. 16.4.10 TIM2 and TIM3 counter (TIM2_CNT and TIM3_CNT) Address offset: 0x24 Reset value: 0x00000000 CNT[31:16] (TIM2 only) CNT[15:0]...
Page 346: Tim2 And Tim3 Capture/Compare Register
General-purpose timers (TIM2 and TIM3) RM0091 16.4.13 TIM2 and TIM3 capture/compare register 1 (TIM2_CCR1 and TIM3_CCR1) Address offset: 0x34 Reset value: 0x00000000 CCR1[31:16] (TIM2 only) CCR1[15:0] Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2). Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 347 RM0091 General-purpose timers (TIM2 and TIM3) Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2). Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 348: Tim2 And Tim3 Capture/Compare Register
General-purpose timers (TIM2 and TIM3) RM0091 16.4.15 TIM2 and TIM3 capture/compare register 3 (TIM2_CCR3 and TIM3_CCR3) Address offset: 0x3C Reset value: 0x00000000 CCR3[31:16] (TIM2 only) CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2). Bits 15:0 CCR3[15:0]: Low Capture/Compare 3 value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
Page 349: Tim2 And Tim3 Dma Control Register (Tim2_Dcr And Tim3_Dcr)
RM0091 General-purpose timers (TIM2 and TIM3) 16.4.17 TIM2 and TIM3 DMA control register (TIM2_DCR and TIM3_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, always read as 0. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 350 General-purpose timers (TIM2 and TIM3) RM0091 Example of how to use the DMA burst feature In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. This is done in the following steps: Configure the corresponding DMA channel as follows: –...
Page 351: Tim2 And Tim3 Register Map
RM0091 General-purpose timers (TIM2 and TIM3) 16.4.19 TIM2 and TIM3 register map TIM2 and TIM3 registers are mapped as described in the table below: Table 50. TIM2 and TIM3 register map and reset values Offset Register TIM2_CR1 and TIM3_CR1 [1:0] [1:0] 0x00 Reset value...
Page 352 General-purpose timers (TIM2 and TIM3) RM0091 Table 50. TIM2 and TIM3 register map and reset values Offset Register Reserved 0x30 Reset value TIM2_CCR1 and CCR1[31:16] CCR1[15:0] TIM3_CCR1 (TIM2 only) 0x34 Reset value TIM2_CCR2 and CCR2[31:16] CCR2[15:0] TIM3_CCR2 (TIM2 only) 0x38 Reset value TIM2_CCR3 and CCR3[31:16]...
Page 353: General-Purpose Timer (Tim14)
RM0091 General-purpose timer (TIM14) General-purpose timer (TIM14) 17.1 TIM14 introduction The TIM14 general-purpose timer consists of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).
Page 354: Tim14 Functional Description
General-purpose timer (TIM14) RM0091 Figure 137. General-purpose timer block diagram (TIM14) TRGO Internal clock (CK_INT) Enable Trigger counter Controller Autoreload register Stop, Clear CK_PSC CK_CNT prescaler counter CC1I CC1I TI1FP1 output Input filter & IC1PS OC1REF Prescaler Capture/Compare 1 register TIMx_CH1 TIMx_CH1 edge detector...
Page 355: Figure 138. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0091 General-purpose timer (TIM14) Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
Page 356: Counter Modes
General-purpose timer (TIM14) RM0091 17.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register.
Page 357: Figure 141. Counter Timing Diagram, Internal Clock Divided By 2
RM0091 General-purpose timer (TIM14) Figure 141. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 142. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT...
Page 358 General-purpose timer (TIM14) RM0091 Figure 144. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register Write a new value in TIMx_ARR...
Page 359: Clock Source
RM0091 General-purpose timer (TIM14) 17.3.3 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically).
Page 360: Figure 148. Capture/Compare Channel 1 Main Circuit
General-purpose timer (TIM14) RM0091 Figure 148. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/compare preload register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/compare shadow register CC1S[0] TIM1_CCMR1 (from time...
Page 361: Input Capture Mode
RM0091 General-purpose timer (TIM14) 17.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 362: Forced Output Mode
General-purpose timer (TIM14) RM0091 17.3.6 Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write ‘101’...
Page 363: Pwm Mode
RM0091 General-purpose timer (TIM14) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 150.
Page 364: Debug Mode
General-purpose timer (TIM14) RM0091 PWM edge-aligned mode In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’.
Page 365: Tim14 Registers
RM0091 General-purpose timer (TIM14) 17.4 TIM14 registers 17.4.1 TIM14 control register 1 (TIM14_CR1) Address offset: 0x00 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE Res. Res. Res. Res. UDIS Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),...
Page 366: Tim14 Interrupt Enable Register (Tim14_Dier)
General-purpose timer (TIM14) RM0091 17.4.2 TIM14 interrupt enable register (TIM14_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1IE Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled...
Page 367: Tim14 Event Generation Register (Tim14_Egr)
RM0091 General-purpose timer (TIM14) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 368: Tim14 Capture/Compare Mode Register 1 (Tim14_Ccmr1)
General-purpose timer (TIM14) RM0091 17.4.5 TIM14 capture/compare mode register 1 (TIM14_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 369 RM0091 General-purpose timer (TIM14) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: Reserved 11: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
Page 370: Tim14 Capture/Compare Enable Register (Tim14_Ccer)
General-purpose timer (TIM14) RM0091 17.4.6 TIM14 capture/compare enable register (TIM14_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP Res. CC1P CC1E Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
Page 371: Tim14 Counter (Tim14_Cnt)
RM0091 General-purpose timer (TIM14) 17.4.7 TIM14 counter (TIM14_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 17.4.8 TIM14 prescaler (TIM14_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 372: Tim14 Capture/Compare Register 1 (Tim14_Ccr1)
General-purpose timer (TIM14) RM0091 17.4.10 TIM14 capture/compare register 1 (TIM14_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 373: Tim14 Register Map
RM0091 General-purpose timer (TIM14) 17.4.12 TIM14 register map TIM14 registers are mapped as 16-bit addressable registers as described in the table below: Table 52. TIM14 register map and reset values Offset Register TIM14_CR1 [1:0] 0x00 Reset value Reserved 0x08 Reset value TIM14_DIER 0x0C Reset value...
Page 374 General-purpose timer (TIM14) RM0091 Table 52. TIM14 register map and reset values (continued) Offset Register TIM14_OR 0x50 Reset value 374/742 Doc ID 018940 Rev 1...
Page 375: General-Purpose Timers (Tim15/16/17)
RM0091 General-purpose timers (TIM15/16/17) General-purpose timers (TIM15/16/17) 18.1 TIM15/16/17 introduction The TIM15/16/17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 376: Tim16 And Tim17 Main Features
General-purpose timers (TIM15/16/17) RM0091 18.3 TIM16 and TIM17 main features The TIM16 and TIM17 timers include the following features: ● 16-bit auto-reload upcounter ● 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 ●...
Page 377: Figure 152. Tim15 Block Diagram
RM0091 General-purpose timers (TIM15/16/17) Figure 152. TIM15 block diagram Internal clock (CK_INT) CK_TIM1121314151617 from RCC Trigger controller TRGO to other timers ITR0 ITR1 Slave ITR2 Reset, enable, up, count mode TRGI controller ITR3 TI1F_ED TI1FP1 TI2FP2 REP register Auto-reload register Repetition counter Stop, clear...
Page 378: Figure 153. Tim16 And Tim17 Block Diagram
General-purpose timers (TIM15/16/17) RM0091 Figure 153. TIM16 and TIM17 block diagram Internal clock (CK_INT) CK_TIM1151617 from RCC Trigger controller TRGO to other timers TI1F_ED Slave Reset, enable, up, count mode TRGI controller TI1FP1 TI2FP2 REP register Auto-reload register Repetition counter Stop, clear up/down CK_PSC...
Page 379: Tim15/16/17 Functional Description
RM0091 General-purpose timers (TIM15/16/17) 18.4 TIM15/16/17 functional description 18.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 380: Counter Modes
General-purpose timers (TIM15/16/17) RM0091 Figure 154. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 155.
Page 381: Figure 156. Counter Timing Diagram, Internal Clock Divided By 1
RM0091 General-purpose timers (TIM15/16/17) The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change).
Page 382: Figure 158. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM15/16/17) RM0091 Figure 158. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 159. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 383: Repetition Counter
RM0091 General-purpose timers (TIM15/16/17) Figure 161. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register Write a new value in TIMx_ARR...
Page 384: Clock Sources
General-purpose timers (TIM15/16/17) RM0091 Figure 162. Update rate examples depending on mode and TIMx_RCR register settings Edge-aligned mode Upcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR re-synchronization (by SW) Update Event: Preload registers transferred to active registers and update interrupt generated ai17332 18.4.4 Clock sources...
Page 385: Figure 163. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0091 General-purpose timers (TIM15/16/17) Figure 163. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 32 33 34 35 36 01 02 03 04 05 06 07 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register.
Page 386: Capture/Compare Channels
General-purpose timers (TIM15/16/17) RM0091 Figure 165. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 18.4.5 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 387: Figure 167. Capture/Compare Channel 1 Main Circuit
RM0091 General-purpose timers (TIM15/16/17) Figure 167. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/compare preload register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/compare shadow register CC1S[0] TIM1_CCMR1 (from time...
Page 388: Input Capture Mode
General-purpose timers (TIM15/16/17) RM0091 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 389: Pwm Input Mode (Only For Tim15)
RM0091 General-purpose timers (TIM15/16/17) Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. 18.4.7 PWM input mode (only for TIM15) This mode is a particular case of input capture mode. The procedure is the same except: ●...
Page 390: Forced Output Mode
General-purpose timers (TIM15/16/17) RM0091 18.4.8 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 391: Pwm Mode
RM0091 General-purpose timers (TIM15/16/17) Procedure: Select the counter clock (internal, external, prescaler). Write the desired data in the TIMx_ARR and TIMx_CCRx registers. Set the CCxIE bit if an interrupt request is to be generated. Select the output mode. For example: –...
Page 392: Figure 172. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM15/16/17) RM0091 OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details.
Page 393: Complementary Outputs And Dead-Time Insertion
RM0091 General-purpose timers (TIM15/16/17) 18.4.11 Complementary outputs and dead-time insertion The TIM15/16/17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN)
Page 394: Using The Break Function
General-purpose timers (TIM15/16/17) RM0091 Figure 175. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 18.5.15: TIM15 break and dead-time register (TIM15_BDTR) on page 417 for delay calculation.
Page 395 RM0091 General-purpose timers (TIM15/16/17) Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals.
Page 396: Figure 176. Output Behavior In Response To A Break
General-purpose timers (TIM15/16/17) RM0091 Figure 176. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 397: One-Pulse Mode
RM0091 General-purpose timers (TIM15/16/17) 18.4.13 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 398 General-purpose timers (TIM15/16/17) RM0091 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ● The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 399: Tim15 External Trigger Synchronization
RM0091 General-purpose timers (TIM15/16/17) 18.4.14 TIM15 external trigger synchronization The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 400: Figure 179. Control Circuit In Gated Mode
General-purpose timers (TIM15/16/17) RM0091 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 401: Timer Synchronization (Tim15)
RM0091 General-purpose timers (TIM15/16/17) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 402: Tim15 Registers
General-purpose timers (TIM15/16/17) RM0091 18.5 TIM15 registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. 18.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 Res. Res. Res. Res. Res. Res.
Page 403: Tim15 Control Register 2 (Tim15_Cr2)
RM0091 General-purpose timers (TIM15/16/17) Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 18.5.2 TIM15 control register 2 (TIM15_CR2) Address offset: 0x04...
Page 404: Tim15 Slave Mode Control Register (Tim15_Smcr)
General-purpose timers (TIM15/16/17) RM0091 Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
Page 405: Table 53. Timx Internal Trigger Connection
RM0091 General-purpose timers (TIM15/16/17) Bits 6:4 TS[2:0]: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2)
Page 406: Tim15 Dma/Interrupt Enable Register (Tim15_Dier)
General-purpose timers (TIM15/16/17) RM0091 18.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. CC2DE CC1DE COMIE Res. Res. CC2IE CC1IE Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bits 13:11...
Page 407: Tim15 Status Register (Tim15_Sr)
RM0091 General-purpose timers (TIM15/16/17) 18.5.5 TIM15 status register (TIM15_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. CC2OF CC1OF Res. COMIF Res. Res. CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, always read as 0. Bit 10 CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag...
Page 408: Tim15 Event Generation Register (Tim15_Egr)
General-purpose timers (TIM15/16/17) RM0091 Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 409: Tim15 Capture/Compare Mode Register 1 (Tim15_Ccmr1)
RM0091 General-purpose timers (TIM15/16/17) Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output.
Page 410 General-purpose timers (TIM15/16/17) RM0091 Output compare mode: Bit 15 Reserved, always read as 0. Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 411 RM0091 General-purpose timers (TIM15/16/17) Bit 2 OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON.
Page 412: Tim15 Capture/Compare Enable Register (Tim15_Ccer)
General-purpose timers (TIM15/16/17) RM0091 Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 413 RM0091 General-purpose timers (TIM15/16/17) Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high 1: OC1N active low Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00”...
Page 414: Table 54. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
General-purpose timers (TIM15/16/17) RM0091 Table 54. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven Output Disabled (not driven by by the timer) the timer)
Page 415: Tim15 Counter (Tim15_Cnt)
RM0091 General-purpose timers (TIM15/16/17) 18.5.9 TIM15 counter (TIM15_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 18.5.10 TIM15 prescaler (TIM15_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1).
Page 416: Tim15 Repetition Counter Register (Tim15_Rcr)
General-purpose timers (TIM15/16/17) RM0091 18.5.12 TIM15 repetition counter register (TIM15_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, always read as 0. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 417: Tim15 Capture/Compare Register 2 (Tim15_Ccr2)
RM0091 General-purpose timers (TIM15/16/17) 18.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 418 General-purpose timers (TIM15/16/17) RM0091 Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 419: Tim15 Dma Control Register (Tim15_Dcr)
RM0091 General-purpose timers (TIM15/16/17) Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 420: Tim15 Dma Address For Full Transfer (Tim15_Dmar)
General-purpose timers (TIM15/16/17) RM0091 18.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 421 RM0091 General-purpose timers (TIM15/16/17) Table 55. TIM15 register map and reset values (continued) Offset Register TIM15_PSC PSC[15:0] 0x28 Reset value TIM15_ARR ARR[15:0] 0x2C Reset value TIM15_RCR REP[7:0] 0x30 Reset value TIM15_CCR1 CCR1[15:0] 0x34 Reset value TIM15_CCR2 CCR2[15:0] 0x38 Reset value LOCK TIM15_BDTR DT[7:0]...
Page 422: Tim16 And Tim17 Registers
General-purpose timers (TIM15/16/17) RM0091 18.6 TIM16 and TIM17 registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. 18.6.1 TIM16 and TIM17 control register 1 (TIM16_CR1 and TIM17_CR1) Address offset: 0x00 Reset value: 0x0000 Res.
Page 423: Tim16 And Tim17 Control Register 2 (Tim16_Cr2 And Tim17_Cr2)
RM0091 General-purpose timers (TIM15/16/17) Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 18.6.2 TIM16 and TIM17 control register 2 (TIM16_CR2 and TIM17_CR2) Address offset: 0x04...
Page 424: Tim16 And Tim17 Dma/Interrupt Enable Register
General-purpose timers (TIM15/16/17) RM0091 18.6.3 TIM16 and TIM17 DMA/interrupt enable register (TIM16_DIER and TIM17_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. CC1DE COMIE Res. Res. Res. CC1IE Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bist 13:10 Reserved, always read as 0.
Page 425: Tim16 And Tim17 Status Register (Tim16_Sr And Tim17_Sr)
RM0091 General-purpose timers (TIM15/16/17) 18.6.4 TIM16 and TIM17 status register (TIM16_SR and TIM17_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. CC1OF Res. COMIF Res. Res. Res. CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, always read as 0. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
Page 426: Tim16 And Tim17 Event Generation Register
General-purpose timers (TIM15/16/17) RM0091 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 427: Tim16 And Tim17 Capture/Compare Mode Register
RM0091 General-purpose timers (TIM15/16/17) Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 428 General-purpose timers (TIM15/16/17) RM0091 Output compare mode: Bits 15:7 Reserved, always read as 0. Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 429 RM0091 General-purpose timers (TIM15/16/17) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 430: Tim16 And Tim17 Capture/Compare Enable Register
General-purpose timers (TIM15/16/17) RM0091 18.6.7 TIM16 and TIM17 capture/compare enable register (TIM16_CCER and TIM17_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP CC1NE CC1P CC1E Bits 15:4 Reserved, always read as 0. Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high 1: OC1N active low...
Page 431 RM0091 General-purpose timers (TIM15/16/17) Table 56. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not Output Disabled (not driven by driven by the timer) the timer) OCx=0, OCx_EN=0...
Page 432: Tim16 And Tim17 Counter (Tim16_Cnt And Tim17_Cnt)
General-purpose timers (TIM15/16/17) RM0091 18.6.8 TIM16 and TIM17 counter (TIM16_CNT and TIM17_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 18.6.9 TIM16 and TIM17 prescaler (TIM16_PSC and TIM17_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1).
Page 433: Tim16 And Tim17 Repetition Counter Register
RM0091 General-purpose timers (TIM15/16/17) 18.6.11 TIM16 and TIM17 repetition counter register (TIM16_RCR and TIM17_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, always read as 0. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 434: Tim16 And Tim17 Break And Dead-Time Register
General-purpose timers (TIM15/16/17) RM0091 18.6.13 TIM16 and TIM17 break and dead-time register (TIM16_BDTR and TIM17_BDTR) Address offset: 0x44 Reset value: 0x0000 OSSR OSSI LOCK[1:0] DTG[7:0] Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Page 435 RM0091 General-purpose timers (TIM15/16/17) Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 18.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page...
Page 436: Tim16 And Tim17 Dma Control Register (Tim16_Dcr And Tim17_Dcr)
General-purpose timers (TIM15/16/17) RM0091 18.6.14 TIM16 and TIM17 DMA control register (TIM16_DCR and TIM17_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, always read as 0. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e.
Page 437 RM0091 General-purpose timers (TIM15/16/17) Example of how to use the DMA burst feature In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. This is done in the following steps: Configure the corresponding DMA channel as follows: –...
Page 438: Tim16 And Tim17 Register Map
General-purpose timers (TIM15/16/17) RM0091 18.6.16 TIM16 and TIM17 register map TIM16 and TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 57. TIM16 and TIM17 register map and reset values Offset Register TIM16_CR1 and 0x00 TIM17_CR1 [1:0]...
Page 439 RM0091 General-purpose timers (TIM15/16/17) Table 57. TIM16 and TIM17 register map and reset values (continued) Offset Register TIM16_DCR and DBL[4:0] DBA[4:0] TIM17_DCR 0x48 Reset value TIM16_DMAR DMAB[15:0] 0x4C TIM17_DMAR Reset value Refer to Section 2.2.2 on page 37 for the register boundary addresses. Doc ID 018940 Rev 1 439/742...
Page 440: Basic Timer (Tim6)
Basic timer (TIM6) RM0091 Basic timer (TIM6) 19.1 TIM6 introduction The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used as a generic timer for time-base generation but it is also specifically used to drive the digital-to-analog converter (DAC).
Page 441: Tim6 Functional Description
RM0091 Basic timer (TIM6) 19.3 TIM6 functional description 19.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 442: Figure 182. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timer (TIM6) RM0091 Figure 182. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 183.
Page 443: Counter Modes
RM0091 Basic timer (TIM6) 19.3.2 Counter modes The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 444: Figure 185. Counter Timing Diagram, Internal Clock Divided By 2
Basic timer (TIM6) RM0091 Figure 185. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 186. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT...
Page 445 RM0091 Basic timer (TIM6) Figure 188. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register...
Page 446: Clock Source
Basic timer (TIM6) RM0091 19.3.3 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically).
Page 447: Tim6 Registers
RM0091 Basic timer (TIM6) 19.4 TIM6 registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 19.4.1 TIM6 control register 1 (TIM6_CR1) Address offset: 0x00 Reset value: 0x0000 Res.
Page 448: Tim6 Control Register 2 (Tim6_Cr2)
Basic timer (TIM6) RM0091 19.4.2 TIM6 control register 2 (TIM6_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 449: Tim6 Status Register (Tim6_Sr)
RM0091 Basic timer (TIM6) 19.4.4 TIM6 status register (TIM6_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event.
Page 450: Tim6 Prescaler (Tim6_Psc)
Basic timer (TIM6) RM0091 19.4.7 TIM6 prescaler (TIM6_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded into the active prescaler register at each update event. 19.4.8 TIM6 auto-reload register (TIM6_ARR) Address offset: 0x2C...
Page 451: Tim6 Register Map
RM0091 Basic timer (TIM6) 19.4.9 TIM6 register map TIM6 registers are mapped as 16-bit addressable registers as described in the table below: Table 58. TIM6 register map and reset values Offset Register TIM6_CR1 0x00 Reset value TIM6_CR2 MMS[2:0] 0x04 Reset value Reserved 0x08 Reset value...
Page 452: Infrared (Irtim) Interface
Infrared (IRTIM) interface RM0091 Infrared (IRTIM) interface An infrared interface (IRTIM) for remote control is available on the device. It can be used with an IR LED to perform remote control functions. To generate the infrared remote control signals, the IR interface must be enabled and TIM16 channel 1 (TIM16_OC1) and TIM17 channel 1 (TIM17_OC1) must be properly configured to generate correct waveforms.
Page 453: Independent Watchdog (Iwdg)
RM0091 Independent watchdog (IWDG) Independent watchdog (IWDG) 21.1 Introduction The devices feature an embedded watchdog peripheral which offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral serves to detect and resolve malfunctions due to software failure, and to trigger system reset when the counter reaches a given timeout value.
Page 454: Hardware Watchdog
Independent watchdog (IWDG) RM0091 Configuring the IWDG when the window option is enabled Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register. Enable register access by writing 0x0000 5555 in the IWDG_KR register. Write the IWDG prescaler by programming IWDG_PR from 0 to 7. Write the reload register (IWDG_RLR).
Page 455: Iwdg Registers
RM0091 Independent watchdog (IWDG) Figure 192. Independent watchdog block diagram CORE Prescaler register Status register Reload register Key register IWDG_PR IWDG_SR IWDG_RLR IWDG_KR 12-bit reload value 8-bit prescaler IWDG reset 12-bit downcounter V DD voltage domain MS19944V1 Note: The watchdog function is implemented in the CORE voltage domain that is still functional in Stop and Standby modes.
Page 456: Prescaler Register (Iwdg_Pr)
Independent watchdog (IWDG) RM0091 21.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 457: Reload Register (Iwdg_Rlr)
RM0091 Independent watchdog (IWDG) 21.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 458: Status Register (Iwdg_Sr)
Independent watchdog (IWDG) RM0091 21.4.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 459: Window Register (Iwdg_Winr)
RM0091 Independent watchdog (IWDG) 21.4.5 Window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WIN[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 460: Iwdg Register Map
Independent watchdog (IWDG) RM0091 21.4.6 IWDG register map The following table gives the IWDG register map and reset values. Table 59. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] 0x00 Reset value IWDG_PR PR[2:0] 0x04 Reset value IWDG_RLR RL[11:0] 0x08 Reset value...
Page 461: System Window Watchdog (Wwdg)
RM0091 System window watchdog (WWDG) System window watchdog (WWDG) 22.1 WWDG introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.
Page 462: Figure 193. Watchdog Block Diagram
System window watchdog (WWDG) RM0091 Figure 193. Watchdog block diagram Watchdog configuration register (WWDG_CFR) RESET comparator = 1 when T6:0 > W6:0 Write WWDG_CR Watchdog control register (WWDG_CR) WDGA 6-bit downcounter (CNT) PCLK (from RCC clock controller) WDG prescaler (WDGTB) The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset.
Page 463: How To Program The Watchdog Timeout
RM0091 System window watchdog (WWDG) case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. Note: When the EWI interrupt cannot be served, e.g.
Page 464: Debug Mode
System window watchdog (WWDG) RM0091 22.5 Debug mode When the microcontroller enters debug mode (Cortex-M0 core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 30.16.2: Debug support for timers, watchdog, bxCAN and I2C.
Page 465: Wwdg Registers
RM0091 System window watchdog (WWDG) 22.6 WWDG registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 22.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Res.
Page 466: Configuration Register (Wwdg_Cfr)
System window watchdog (WWDG) RM0091 22.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WDGTB[1:0] W[6:0] Bit 31:10 Reserved, must be kept at reset value.
Page 467: Wwdg Register Map
RM0091 System window watchdog (WWDG) 22.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 60. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reset value WWDG_CFR W[6:0] 0x04 Reset value WWDG_SR 0x08 Reset value...
Page 468: Inter-Integrated Circuit (I 2 C) Interface
Inter-integrated circuit (I C) interface RM0091 Inter-integrated circuit (I C) interface 23.1 C introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing.
Page 469: I2C Implementation
RM0091 Inter-integrated circuit (I C) interface ● PMBus rev 1.1 standard compatibility ● Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming ● Wakeup from STOP on address match. 23.3 I2C implementation This manual describes the full set of features implemented in I2C1.
Page 470: I2C1 Block Diagram
Inter-integrated circuit (I C) interface RM0091 23.4.1 I2C1 block diagram The block diagram of the I C1 interface is shown in Figure 195. Figure 195. I C1 block diagram SYSCLK I2CCLK From system configuration controller (SYSCFG) FM+ drive Data control Digital Analog Shift register...
Page 471: I2C2 Block Diagram
RM0091 Inter-integrated circuit (I C) interface 23.4.2 I2C2 block diagram The block diagram of the I C2 interface is shown in Figure 195. Figure 196. I C2 block diagram Data control Digital PCLK Analog Shift register noise noise GPIO I2C2_SDA filter filter logic...
Page 472: Mode Selection
Inter-integrated circuit (I C) interface RM0091 23.4.4 Mode selection The interface can operate in one of the four following modes: ● Slave transmitter ● Slave receiver ● Master transmitter ● Master receiver By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability.
Page 473: I 2 C Initialization
RM0091 Inter-integrated circuit (I C) interface 23.4.5 C initialization Enabling and disabling the peripheral The I2C peripheral clock must be configured and enabled in the clock controller (refer to the RCC Clocks section. Then the I2C can be enabled by setting the PE bit in the I2Cx_CR1 register. When the I2C is disabled (PE=0), the I2C performs a software reset: I2C lines (SDA and SCL) are released.
Page 474: Figure 198. Setup And Hold Timings
Inter-integrated circuit (I C) interface RM0091 Figure 198. Setup and hold timings DATA HOLD TIME SCL falling edge internal detection SDADEL SYNC1 SDA output delay t h(SDA) Data hold time DATA SETUP TIME SCLDEL SCL stretched low by the slave transmitter tsu (SDA) Data setup time MS19846V1...
Page 475: Table 64. I2C-Smbus Specification Data Setup And Hold Times
RM0091 Inter-integrated circuit (I C) interface SDADEL <= {t -260 ns - [(DNF+3) x t ]} / {(PRESC +1) x t HD;DAT (max) I2CCLK I2CCLK Note: -50 ns / -260 ns are part of the equation only when the analog filter is enabled. Refer to Table 64.: I2C-SMBUS specification data setup and hold times for t...
Page 476: Software Reset
Inter-integrated circuit (I C) interface RM0091 Figure 199. I2C initialization flowchart Initial settings Clear PE bit in I2Cx_CR1 Configure ANFOFF and DNF[3:0] in I2Cx_CR1 Configure PRESC[3:0], SDADEL[3:0], SCLDEL[3:0], SCLH[7:0], SCLL[7:0] in I2Cx_TIMINGR Configure NOSTRETCH in I2Cx_CR1 Set PE bit in I2Cx_CR1 MS19847V1 23.4.6 Software reset...
Page 477: Data Transfer
RM0091 Inter-integrated circuit (I C) interface 23.4.7 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into I2Cx_RXDR register if it is empty (RXNE=0).
Page 478: Figure 201. Data Transmission
Inter-integrated circuit (I C) interface RM0091 Figure 201. Data transmission ACK pulse ACK pulse legend: stretch Shift register wr data1 wr data2 I2C_TXDR data0 data1 data2 MS19849V1 Hardware transfer management The I2C has a byte counter embedded in hardware in order to manage byte transfer and to close the communication in various modes such as: –...
Page 479: I2C Slave Mode
RM0091 Inter-integrated circuit (I C) interface Caution: The AUTOEND bit has no effect when the RELOAD bit is set. Table 65. I2C Configuration table Function SBC bit RELOAD bit AUTOEND bit Master Tx/Rx NBYTES + STOP Master Tx/Rx + NBYTES + RESTART Slave Tx/Rx all received bytes ACKed Slave Rx with ACK control...
Page 480 Inter-integrated circuit (I C) interface RM0091 Slave clock stretching (NOSTRETCH = 0) In default mode, the I2C slave stretches the SCL clock in the following situations: ● When the ADDR flag is set: the received address matches with one of the enabled slave addresses.
Page 481: Figure 202. Slave Initialization Flowchart
RM0091 Inter-integrated circuit (I C) interface Note: The SBC bit must be configured when the I2C is disabled, or when the slave is not addressed, or when ADDR=1. The RELOAD bit value can be changed when ADDR=1, or when TCR=1. Caution: Slave Byte Control mode is not compatible with NOSTRETCH mode.
Page 482 Inter-integrated circuit (I C) interface RM0091 When a STOP is received and the STOPIE bit is set in the I2Cx_CR1 register, the STOPF flag is set in the I2Cx_ISR register and an interrupt is generated. In most applications, the SBC bit is usually programmed to ‘0’. In this case, If TXE = 0 when the slave address is received (ADDR=1), you can choose either to send the content of the I2Cx_TXDR register as the first data byte, or to flush the I2Cx_TXDR register by setting the TXE bit in order to program a new data byte.
Page 483: Figure 203. Transfer Sequence Flowchart For I2C Slave Transmitter, Nostretch=0
RM0091 Inter-integrated circuit (I C) interface Figure 203. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0 Slave transmission Slave initialization I2Cx_ISR.ADDR stretched Read ADDCODE and DIR in I2Cx_ISR Optional: Set I2Cx_ISR.TXE = 1 Set I2Cx_ICR.ADDRCF I2Cx_ISR.TXIS Write I2Cx_TXDR.TXDATA Figure 204. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1 Slave transmission Slave initialization...
Page 484: Figure 205. Transfer Bus Diagrams For I2C Slave Transmitter
Inter-integrated circuit (I C) interface RM0091 Figure 205. Transfer bus diagrams for I2C slave transmitter legend: Example I2C slave transmitter 3 bytes with 1st data flushed, NOSTRETCH=0: transmission ADDR TXIS TXIS TXIS TXIS reception SCL stretch data1 data2 data3 Address EV4 EV5 EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF EV2: TXIS ISR: wr data1...
Page 485: Figure 206. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
RM0091 Inter-integrated circuit (I C) interface Slave receiver RXNE is set in I2Cx_ISR when the I2Cx_RXDR is full, and generates an interrupt if RXIE is set in I2Cx_CR1. RXNE is cleared when I2Cx_RXDR is read. When a STOP is received and STOPIE is set in I2Cx_CR1, STOPF is set in I2Cx_ISR and an interrupt is generated.
Page 486: Figure 207. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
Inter-integrated circuit (I C) interface RM0091 Figure 207. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Slave reception Slave initialization I2Cx_ISR.RXNE I2Cx_ISR.STOPF Set I2Cx_ICR.STOPCF Read I2Cx_RXDR.RXDATA MS19856V1 Figure 208. Transfer bus diagrams for I2C slave receiver transmission ADDR RXNE RXNE RXNE reception SCL stretch...
Page 487: I2C Master Mode
RM0091 Inter-integrated circuit (I C) interface 23.4.9 C master mode I2C master initialization Before enabling the peripheral, the I2C master clock must be configured by setting the SCLH and SCLL bits in the I2Cx_TIMINGR register. A clock synchronization mechanism is implemented in order to support multi-master environment and slave clock stretching.
Page 488: Table 66. I2C-Smbus Specification Clock Timings
Inter-integrated circuit (I C) interface RM0091 Figure 209. Master clock generation SCL master clock generation SCL high level detected SCLH counter starts SYNC2 SCLH SCLL SYNC1 SCL low level detected SCL released SCLL counter starts SCL driven low SCL master clock synchronization SCL high level detected SCL high level detected SCL high level detected...
Page 489 RM0091 Inter-integrated circuit (I C) interface Table 66. I2C-SMBUS specification clock timings (continued) Fast Mode Standard Fast Mode SMBUS Plus Symbol Parameter Unit Bus free time between a µs STOP and START condition µs Low period of the SCL clock 0.26 µs Period of the SCL clock...
Page 490: Figure 210. Master Initialization Flowchart
Inter-integrated circuit (I C) interface RM0091 Figure 210. Master initialization flowchart Master initialization Initial settings Enable interrupts and/or DMA in I2Cx_CR1 MS19859V1 Initialization of a master receiver addressing a 10-bit address slave ● If the slave address is in 10-bit format, you can choose to send the complete read sequence by clearing the HEAD10R bit in the I2Cx_CR2 register.
Page 491: Figure 212. 10-Bit Address Read Access With Head10R=1
RM0091 Inter-integrated circuit (I C) interface Figure 212. 10-bit address read access with HEAD10R=1 1 1 1 1 0 X X Slave address Slave address DATA DATA 1st 7 bits 2nd byte Write 1 1 1 1 0 X X Slave address DATA DATA...
Page 492: Figure 213. Transfer Sequence Flowchart For I2C Master Transmitter For N<=255 Bytes
Inter-integrated circuit (I C) interface RM0091 Figure 213. Transfer sequence flowchart for I2C master transmitter for N<=255 bytes Master transmission Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set I2Cx_CR2.START I2Cx_ISR.TXIS I2Cx_ISR.NACKF = 1? Write I2Cx_TXDR NBYTES...
Page 493: Figure 214. Transfer Sequence Flowchart For I2C Master Transmitter For N>255 Bytes
RM0091 Inter-integrated circuit (I C) interface Figure 214. Transfer sequence flowchart for I2C master transmitter for N>255 bytes Master transmission Master initialization NBYTES = 0xFF; N=N-255 RELOAD =1 Configure slave address Set I2Cx_CR2.START I2Cx_ISR.TXIS I2Cx_ISR.NACKF = 1? Write I2Cx_TXDR NBYTES transmitted? I2Cx_ISR.TC = 1?
Page 494: Figure 215. Transfer Bus Diagrams For I2C Master Transmitter
Inter-integrated circuit (I C) interface RM0091 Figure 215. Transfer bus diagrams for I2C master transmitter legend: Example I2C master transmitter 2 bytes, automatic end mode (STOP) transmission TXIS TXIS reception SCL stretch data1 data2 Address INIT EV1 EV2 NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: TXIS ISR: wr data1 EV2: TXIS ISR: wr data2 Example I2C master transmitter 2 bytes, software end mode (RESTART)
Page 495 RM0091 Inter-integrated circuit (I C) interface Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2Cx_CR1 register.
Page 496: Figure 216. Transfer Sequence Flowchart For I2C Master Receiver For N<=255 Bytes
Inter-integrated circuit (I C) interface RM0091 Figure 216. Transfer sequence flowchart for I2C master receiver for N<=255 bytes Master reception Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set I2Cx_CR2.START I2Cx_ISR.RXNE Read I2Cx_RXDR NBYTES received? I2Cx_ISR.TC...
Page 497: Figure 217. Transfer Sequence Flowchart For I2C Master Receiver For N>255 Bytes
RM0091 Inter-integrated circuit (I C) interface Figure 217. Transfer sequence flowchart for I2C master receiver for N>255 bytes Master reception Master initialization NBYTES = 0xFF; N=N-255 RELOAD =1 Configure slave address Set I2Cx_CR2.START I2Cx_ISR.RXNE Read I2Cx_RXDR NBYTES received? I2Cx_ISR.TC = 1? Set I2Cx_CR2.START with slave addess NBYTES ...
Page 498: Figure 218. Transfer Bus Diagrams For I2C Master Receiver
Inter-integrated circuit (I C) interface RM0091 Figure 218. Transfer bus diagrams for I2C master receiver Example I2C master receiver 2 bytes, automatic end mode (STOP) RXNE RXNE legend: transmission data1 data2 Address reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 Example I2C master receiver 2 bytes, software end mode (RESTART)
Page 499: I2Cx_Timingr Register Configuration Examples
RM0091 Inter-integrated circuit (I C) interface 23.4.10 I2Cx_TIMINGR register configuration examples Table 67. Examples of timings settings for f = 8 MHz I2CCLK Standard mode Fast Mode Fast Mode Plus Parameter 10 kHz 100 kHz 400 kHz 500 kHz PRESC SCLL 0xC7 0x13...
Page 500: Table 69. Examples Of Timings Settings For Fi2Cclk = 48 Mhz
Inter-integrated circuit (I C) interface RM0091 Table 69. Examples of timings settings for f = 48 MHz I2CCLK Standard mode Fast Mode Fast Mode Plus Parameter 10 kHz 100 kHz 400 kHz 1000 kHz PRESC SCLL 0xC7 0x13 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 4 x 125 ns = 500 ns...
Page 501: Smbus Specific Features
RM0091 Inter-integrated circuit (I C) interface 23.4.11 SMBus specific features This section is relevant only when SMBus feature is supported. Please refer to Table 23.3: implementation. Introduction The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on I2C principles of operation.
Page 502 Inter-integrated circuit (I C) interface RM0091 Received Command and Data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in I2Cx_CR1 register.
Page 503: Table 70. Table
RM0091 Inter-integrated circuit (I C) interface Table 70. SMBus timeout specifications Limits Symbol Parameter Unit Detect clock low timeout TIMEOUT Cumulative clock low extend time (slave LOW:SEXT device) Cumulative clock low extend time (master LOW:MEXT device) 1. t is the cumulative time a given slave device is allowed to extend the clock cycles in one LOW:SEXT message from the initial START to the STOP.
Page 504: Smbus Initialization
Inter-integrated circuit (I C) interface RM0091 SMBus 23.4.12 initialization This section is relevant only when SMBus feature is supported. Please refer to Section 23.3: implementation. In addition to I2C initialization, some other specific initialization must be done in order to perform SMBus communication: Received Command and Data Acknowledge control (Slave mode) A SMBus receiver must be able to NACK each received command or data.
Page 505: Smbus: I2Cx_Timeoutr Register Configuration Examples
RM0091 Inter-integrated circuit (I C) interface Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the I2Cx_TIMEOUTR register. The timers must be programmed in such a way that they detect a timeout before the maximum time given in the SMBus specification ver. 2.0. ●...
Page 506: Smbus Slave Mode
Inter-integrated circuit (I C) interface RM0091 Table 72. Examples of TIMEOUTA settings for various I2CCLK frequencies TIDLE TIMEOUTA[11:0] TIMEOUTEN I2CCLK TIMEOUT bits 8 MHz 0x61 98 x 2048 x 125 ns = 25 ms 16 MHz 0xC3 196 x 2048 x 62.5 ns = 25 ms 48 MHz 0x249 586 x 2048 x 20.08 ns = 25 ms...
Page 507: Figure 220. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec
RM0091 Inter-integrated circuit (I C) interface Figure 220. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC SMBus slave transmission Slave initialization I2Cx_ISR.ADDR = Read ADDCODE and DIR in I2Cx_ISR stretched I2Cx_CR2.NBYTES = N + 1 PECBYTE=1 Set I2Cx_ICR.ADDRCF I2Cx_ISR.TXIS Write I2Cx_TXDR.TXDATA MS19867V1...
Page 508 Inter-integrated circuit (I C) interface RM0091 SMBus Slave receiver When the I2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the Slave ACK control of each byte, the reload mode must be selected (RELOAD=1).
Page 509: Figure 222. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
RM0091 Inter-integrated circuit (I C) interface Figure 222. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC SMBus slave reception Slave initialization I2Cx_ISR.ADDR = Read ADDCODE and DIR in I2Cx_ISR stretched I2Cx_CR2.NBYTES = 1, RELOAD =1 PECBYTE=1 Set I2Cx_ICR.ADDRCF I2Cx_ISR.RXNE =1? I2Cx_ISR.TCR = 1? Read I2Cx_RXDR.RXDATA...
Page 510: Figure 223. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
Inter-integrated circuit (I C) interface RM0091 Figure 223. Bus transfer diagrams for SMBus slave receiver (SBC=1) legend: Example SMBus slave receiver 2 bytes + PEC transmission ADDR RXNE RXNE RXNE reception Address data1 data2 SCL stretch NBYTES EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF EV2: RXNE ISR: rd data1 EV3: RXNE ISR: rd data2 EV4: RXNE ISR: rd PEC...
Page 511: Figure 224. Bus Transfer Diagrams For Smbus Master Transmitter
RM0091 Inter-integrated circuit (I C) interface If the SMBus master wants to send a STOP condition after the PEC, automatic end mode should be selected (AUTOEND=1). In this case, the STOP condition automatically follows the PEC transmission. When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0).
Page 512 Inter-integrated circuit (I C) interface RM0091 SMBus Master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit.
Page 513: Wakeup From Stop On Address Match
RM0091 Inter-integrated circuit (I C) interface Figure 225. Bus transfer diagrams for SMBus master receiver Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP) RXNE RXNE RXNE legend: transmission data1 data2 Address reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2...
Page 514: Error Conditions
Inter-integrated circuit (I C) interface RM0091 HSI is then used for the address reception. In case of an address match, the I2C stretches SCL low during MCU wakeup time. The stretch is released when ADDR flag is cleared by software, and the transfer goes on normally.
Page 515 RM0091 Inter-integrated circuit (I C) interface Overrun/underrun error (OVR) An overrun or underrun error is detected in slave mode when NOSTRETCH=1 and: ● In reception when a new byte is received and the RXDR register has not been read yet. The new received byte is lost, and a NACK is automatically sent as a response to the new byte.
Page 516: Dma Requests
Inter-integrated circuit (I C) interface RM0091 The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN=1), the alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin. An interrupt is generated if the ERRIE bit is set in the I2Cx_CR1 register. 23.4.17 DMA requests Transmission using DMA...
Page 517: I 2 C Interrupts
RM0091 Inter-integrated circuit (I C) interface 23.5 C interrupts The table below gives the list of I C interrupt requests. Table 75. C Interrupt requests Event flag/Interrupt Interrupt enable Interrupt event Event flag clearing method control bit Read I2Cx_RXDR Receive buffer not empty RXNE RXIE register...
Page 518: Figure 226. I2C Interrupt Mapping Diagram
Inter-integrated circuit (I C) interface RM0091 Figure 226. I C interrupt mapping diagram TCIE TXIS TXIE RXNE RXIE I2C event interrupt STOPF STOPIE ADDR I2C global interrupt ADDRIE NACKF NACKIE BERR ARLO TIMEOUT ERRIE ALERT I2C error interrupt PECERR MS19824V1 518/742 Doc ID 018940 Rev 1...
Page 519: I 2 C Debug Mode
RM0091 Inter-integrated circuit (I C) interface 23.6 C debug mode When the microcontroller enters debug mode (core halted), the SMBus timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module.. 23.7 C registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions.
Page 520 Inter-integrated circuit (I C) interface RM0091 Bit 20 SMBHEN: SMBus Host address enable 0: Host address disabled. Address 0b0001000x is NACKed. 1: Host address enabled. Address 0b0001000x is ACKed. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 23.3: I2C implementation.
Page 521 RM0091 Inter-integrated circuit (I C) interface Bit 7 ERRIE: Error interrupts enable 0: Error detection interrupts disabled 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) Bit 6 TCIE: =Transfer Complete interrupt enable...
Page 522: Control Register 2 (I2Cx_Cr2)
Inter-integrated circuit (I C) interface RM0091 23.7.2 Control register 2 (I2Cx_CR2) Address offset: 0x04 Reset value: 0x0000 0000 AUTO Res. Res. Res. Res. Res. NBYTES[7:0] BYTE LOAD HEAD RD_W NACK STOP START ADD10 SADD[9:0] Bits 31:27 Reserved, must be kept at reset value. Bit 26 PECBYTE: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or...
Page 523 RM0091 Inter-integrated circuit (I C) interface Bit 15 NACK: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address Matched is received, or when PE=0 or SWRST is set. 0: an ACK is sent after current received byte.
Page 524: Own Address 1 Register (I2Cx_Oar1)
Inter-integrated circuit (I C) interface RM0091 Bits 9:8 SADD[9:8]: Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are don’t care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed.
Page 525: Own Address 2 Register (I2Cx_Oar2)
RM0091 Inter-integrated circuit (I C) interface Bits 7:1 OA1[7:1]: Interface address bits 7:1 of address Note: These bits can be written only when OA1EN=0. Bit 0 OA1[0]: Interface address 7-bit addressing mode: don’t care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0.
Page 526: Timing Register (I2Cx_Timingr)
Inter-integrated circuit (I C) interface RM0091 23.7.5 Timing register (I2Cx_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period t used for PRESC data setup and hold counters (refer to...
Page 527: Timeout Register (I2Cx_Timeoutr)
RM0091 Inter-integrated circuit (I C) interface 23.7.6 Timeout register (I2Cx_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 TEXTEN Res. Res. Res. TIMEOUTB TIMOUTEN Res. Res. TIDLE TIMEOUTA Bits 31 TEXTEN: Extended clock timeout enable 0: Extended clock timeout detection is disabled 1: Extended clock timeout detection is enabled.
Page 528: Interrupt And Status Register (I2Cx_Isr)
Inter-integrated circuit (I C) interface RM0091 23.7.7 Interrupt and Status register (I2Cx_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS r_w1 r_w1 Bits 31:24 Reserved, must be kept at reset value.
Page 529 RM0091 Inter-integrated circuit (I C) interface Bit 10 OVR: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0 or SWRST is set. Bit 9 ARLO: Arbitration lost This flag is set by hardware when the interface in case of arbitration loss.
Page 530 Inter-integrated circuit (I C) interface RM0091 Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2Cx_RXDR register, and is ready to be read. It is cleared when I2Cx_RXDR is read. Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Page 531: Interrupt Clear Register (I2Cx_Icr)
RM0091 Inter-integrated circuit (I C) interface 23.7.8 Interrupt clear register (I2Cx_ICR) Address offset: 0x1C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ALERT ARLO BERR STOP NACK ADDR Res.
Page 532: Pec Register (I2Cx_Pecr)
Inter-integrated circuit (I C) interface RM0091 23.7.9 PEC register (I2Cx_PECR) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 533: Transmit Data Register (I2Cx_Txdr)
RM0091 Inter-integrated circuit (I C) interface 23.7.11 Transmit data register (I2Cx_TXDR) Address offset: 0x28 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 534: I2C Register Map
Inter-integrated circuit (I C) interface RM0091 23.8 C register map The table below provides the I C register map and reset values. Table 76. C register map and reset values Offset Register I2Cx_CR1 Reset Value I2Cx_CR2 Reset Value I2Cx_OAR1 Reset Value I2Cx_OAR2 Reset Value I2Cx_TIMINGR...
Page 535: Real-Time Clock (Rtc)
RM0091 Real-time clock (RTC) Real-time clock (RTC) 24.1 Introduction The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar with programmable alarm interrupt. The RTC provides an automatic wakeup to manage all low power modes. Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD).
Page 536: Rtc Functional Description
Real-time clock (RTC) RM0091 24.3 RTC functional description 24.3.1 RTC block diagram Figure 227. RTC block diagram Backup registers RTC_TAMP2 and RTC tamper TAMPxF RTC_TAMP1 control registers RTC_TS Time stamp registers RTC_REFIN LSE (32.768 Hz) HSE/32 RTCCLK ck_apre ck_spre RTC_CALR RTC_PRER RTC_PRER (default 256 Hz)
Page 537: Gpios Controlled By The Rtc
RM0091 Real-time clock (RTC) 24.3.2 GPIOs controlled by the RTC RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13). The selection of the RTC_ALARM output is performed through the RTC_TAFCR register as follows: the PC13VALUE bit is used to select whether the RTC_ALARM output is configured in push-pull or open drain mode.
Page 538: Clock And Prescalers
Real-time clock (RTC) RM0091 Table 78. LSE pin PC14 configuration Pin configuration and LSEON bit in LSEBYP bit in PC14MODE PC14VALUE function RCC_BDCR register RCC_BDCR register LSE oscillator Don’t care Don’t care LSE bypass Don’t care Don’t care PC14 output data Output PP forced Don’t care value...
Page 539: Real-Time Clock And Calendar
RM0091 Real-time clock (RTC) The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz. The minimum division factor is 1 and the maximum division factor is 2 This corresponds to a maximum input frequency of around 4 MHz.
Page 540: Rtc Initialization And Configuration
Real-time clock (RTC) RM0091 of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register. Caution: If the seconds field is selected (MSK0 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.
Page 541: Reading The Calendar
RM0091 Real-time clock (RTC) Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its power-on reset default value (0x00). To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register.
Page 542: Resetting The Rtc
Real-time clock (RTC) RM0091 After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values. After an initialization (refer to Calendar initialization and configuration on page 540): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR...
Page 543: Rtc Reference Clock Detection
RM0091 Real-time clock (RTC) 1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution allowed (30.52 µs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF. However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler’s output at 1 Hz.
Page 544: Rtc Smooth Digital Calibration
Real-time clock (RTC) RM0091 When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their default values: ● PREDIV_A = 0x007F ● PREVID_S = 0x00FF Note: RTC_REFIN clock detection is not available in Standby mode. 24.3.11 RTC smooth digital calibration The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1 ppm to +488.5 ppm.
Page 545 RM0091 Real-time clock (RTC) interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less). If PREDIV_S is reduced in this way, the formula given the effective frequency of the calibrated input clock is as follows: x [ 1 + (256 - CALM) / (2 + CALM - 256) ] RTCCLK...
Page 546: Time-Stamp Function
Real-time clock (RTC) RM0091 24.3.12 Time-stamp function Time-stamp is enabled by setting the TSE bit of RTC_CR register to 1. The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a time-stamp event is detected on the RTC_TS pin. When a time-stamp event occurs, the time-stamp flag bit (TSF) in RTC_ISR register is set.
Page 547 RM0091 Real-time clock (RTC) Timestamp on tamper event: With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal timestamp event occurs.
Page 548: Calibration Clock Output
Real-time clock (RTC) RM0091 24.3.14 Calibration clock output When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB frequency is f /64.
Page 549: Rtc Interrupts
RM0091 Real-time clock (RTC) 24.5 RTC interrupts All RTC interrupts are connected to the EXTI controller. Refer to the External and internal interrupt/event line mapping section. To enable the RTC Alarm interrupt, the following sequence is required: Configure and enable the EXTI line corresponding to the RTC Alarm event in interrupt mode and select the rising edge sensitivity.
Page 550: Rtc Registers
Real-time clock (RTC) RM0091 24.6 RTC registers Refer to Section 1.1 on page 34 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 24.6.1 RTC time register (RTC_TR) The RTC_TR is the calendar time shadow register.
Page 551: Rtc Date Register (Rtc_Dr)
RM0091 Real-time clock (RTC) 24.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 540 Reading the calendar on page 541.
Page 552: Rtc Control Register (Rtc_Cr)
Real-time clock (RTC) RM0091 24.6.3 RTC control register (RTC_CR) Address offset: 0x08 Power-on reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL SUB1H ADD1H BYPS TSIE Res. Res. ALRAIE Res. Res. ALRAE Res.
Page 553 RM0091 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Time-stamp interrupt enable 0: Time-stamp Interrupt disable 1: Time-stamp Interrupt enable...
Page 554 Real-time clock (RTC) RM0091 Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1). It is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour. ADD1H and SUB1H changes are effective in the next second.
Page 555: Rtc Initialization And Status Register (Rtc_Isr)
RM0091 Real-time clock (RTC) 24.6.4 RTC initialization and status register (RTC_ISR) This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 540. Address offset: 0x0C Reset value: 0x0000 0007 RECAL Res.
Page 556 Real-time clock (RTC) RM0091 Bit 7 INIT: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. Bit 6 INITF: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
Page 557: Rtc Prescaler Register (Rtc_Prer)
RM0091 Real-time clock (RTC) 24.6.5 RTC prescaler register (RTC_PRER) This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 540 This register is write protected. The write access procedure is described in RTC register write protection on page 540.
Page 558 Real-time clock (RTC) RM0091 Bit 31 MSK4: Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day don’t care in Alarm A comparison Bit 30 WDSEL: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don’t care. Bits 29:28 DT[1:0]: Date tens in BCD format.
Page 559: Rtc Write Protection Register (Rtc_Wpr)
RM0091 Real-time clock (RTC) 24.6.7 RTC write protection register (RTC_WPR) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 560: Rtc Sub Second Register (Rtc_Ssr)
Real-time clock (RTC) RM0091 24.6.8 RTC sub second register (RTC_SSR) Address offset: 0x28 Power-on reset value: 0x0000 0000 System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 561: Rtc Shift Control Register (Rtc_Shiftr)
RM0091 Real-time clock (RTC) 24.6.9 RTC shift control register (RTC_SHIFTR) This register is write protected. The write access procedure is described in RTC register write protection on page 540. Address offset: 0x2C Reset value: 0x0000 0000 ADD1S Res. Res. Res. Res.
Page 562: Rtc Timestamp Time Register (Rtc_Tstr)
Real-time clock (RTC) RM0091 24.6.10 RTC timestamp time register (RTC_TSTR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x30 Power-on reset value: 0x0000 0000 System reset: not affected Res.
Page 563: Rtc Time-Stamp Sub Second Register (Rtc_Tsssr)
RM0091 Real-time clock (RTC) Bits 31:16 Reserved, must be kept at reset value Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value Bits 5:4 DT[1:0]: Date tens in BCD format Bit 3:0 DU[3:0]: Date units in BCD format 24.6.12...
Page 564: Rtc Calibration Register (Rtc_Calr)
Real-time clock (RTC) RM0091 24.6.13 RTC calibration register (RTC_CALR) This register is write protected. The write access procedure is described in RTC register write protection on page 540. Address offset: 0x3C Power-on reset value: 0x0000 0000 System reset: not affected Res.
Page 565: Rtc Tamper And Alternate Function Configuration Register
RM0091 Real-time clock (RTC) 24.6.14 RTC tamper and alternate function configuration register (RTC_TAFCR) Address offset: 0x40 Power-on reset value: 0x0000 0000 System reset: not affected PC15 PC15 PC14 PC14 PC13 PC13 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 566 Real-time clock (RTC) RM0091 Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 0x0: 1 RTCCLK cycle 0x1: 2 RTCCLK cycles 0x2: 4 RTCCLK cycles 0x3: 8 RTCCLK cycles Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count...
Page 567 RM0091 Real-time clock (RTC) Bit 2 TAMPIE: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled. Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input If TAMPFLT != 00 0: RTC_TAMP1 input staying low triggers a tamper detection event. 1: RTC_TAMP1 input staying high triggers a tamper detection event.
Page 568: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
Real-time clock (RTC) RM0091 24.6.15 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 540 Address offset: 0x44...
Page 569: Rtc Backup Registers (Rtc_Bkpxr)
RM0091 Real-time clock (RTC) 24.6.16 RTC backup registers (RTC_BKPxR) Address offset: 0x50 to 0x60 Power-on reset value: 0x0000 0000 System reset: not affected BKP[31:16] BKP[15:0] Bits 31:0 BKP[31:0] The application can write or read data to and from these registers. They are powered-on by V when V is switched off, so that they are not reset by...
Page 570 Real-time clock (RTC) RM0091 Table 82. RTC register map and reset values (continued) Offset Register RTC_SHIFTR SUBFS[14:0] 0x2C Reset value RTC_TSTR HU[3:0] MNU[3:0] ST[2:0] SU[3:0] 0x30 Reset value RTC_TSDR WDU[1:0] MU[3:0] DU[3:0] 0x34 [1:0] Reset value RTC_TSSSR SS[15:0] 0x38 Reset value RTC_ CALR CALM[8:0] 0x3C...
Page 571: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Universal synchronous asynchronous receiver transmitter (USART) 25.1 USART introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a baud rate generator.
Page 572: Usart Extended Features
Universal synchronous asynchronous receiver transmitter (USART) RM0091 ● Parity control: – Transmits parity bit – Checks parity of received data byte ● Four error detection flags: – Overrun error – Noise detection – Frame error – Parity error ● Fourteen interrupt sources with flags –...
Page 573: Usart Implementation
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.4 USART implementation This manual describes the full set of features implemented in USART1. USART2 supports a smaller set of features, but is otherwise identical to USART1. The differences are listed in the following table. Table 83.
Page 574 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word (8 or 9 bits) least significant bit first ●...
Page 575: Figure 228. Usart Block Diagram
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Figure 228. USART block diagram PWDATA PRDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA Receive Shift Register Transmit Shift Register ENDEC block USART_GTPR register...
Page 576: Usart Character Description
Universal synchronous asynchronous receiver transmitter (USART) RM0091 25.5.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 229). In default configuration, the signal (TX or RX) is in low state during the start bit. It is in high state during the stop bit.
Page 577: Transmitter
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.5.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.
Page 578 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Procedure: Program the M bit in USART_CR1 to define the word length. Select the desired baud rate using the USART_BRR register. Program the number of stop bits in USART_CR2. Enable the USART by writing the UE bit in USART_CR1 register to 1. Select DMA enable (DMAT) in USART_CR3 if Multi buffer Communication is to take place.
Page 579: Receiver
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Figure 231. TC/TXE behavior when transmitting Idle preamble Frame 1 Frame 2 Frame 3 TX line set by hardware set by hardware cleared by software cleared by software set by hardware TXE flag USART_DR TC flag by hardware...
Page 580: Figure 232. Start Bit Detection When Oversampling By 16 Or 8
Universal synchronous asynchronous receiver transmitter (USART) RM0091 Figure 232. Start bit detection when oversampling by 16 or 8 RX state Idle Start bit RX line Ideal sample 10 11 12 13 14 15 16 clock sampled values Real 10 11 12 13 14 15 16 sample clock 6/16...
Page 581 RM0091 Universal synchronous asynchronous receiver transmitter (USART) When a character is received ● The RXNE bit is set. It indicates that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags).
Page 582 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Selecting the clock source and the proper oversampling method The choice of the clock source is done through the Clock Control system (see the Reset and clock control (RCC) section). The clock source must be chosen before enabling the USART (by setting the UE bit).
Page 583: Table 84. Noise Detection From Sampled Data
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Tolerance of the USART receiver to clock deviation on page 587). In this case the NF bit will never be set. When noise is detected in a frame: ● The NF bit is set at the rising edge of the RXNE bit. ●...
Page 584 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Table 84. Noise detection from sampled data (continued) Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise.
Page 585: Baud Rate Generation
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.5.4 Baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the USART_BRR register. Equation 1: Baud rate for standard USART (SPI mode included) In case of oversampling by 16, the equation is: Tx/Rx baud --------------------------------...
Page 586: Table 85. Error Calculation For Programmed Baud Rates At F
Universal synchronous asynchronous receiver transmitter (USART) RM0091 Example 2 To obtain 921.6 Kbaud with f = 48 MHz. ● In case of oversampling by 16: USARTDIV = 48 000 000/921 600 BRR = USARTDIV = 52d = 0x34 ● In case of oversampling by 8: USARTDIV = 2 * 48 000 000/921 600 USARTDIV = 104 (104d = 0x68) BRR[3:0] = USARTDIV[3:0] >>...
Page 587: Tolerance Of The Usart Receiver To Clock Deviation
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.5.5 Tolerance of the USART receiver to clock deviation The asynchronous receiver of the USART works correctly only if the total clock system deviation is less than the tolerance of the USART receiver. The causes which contribute to the total deviation are: ●...
Page 588: Auto Baud Rate Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0091 Table 87. Tolerance of the USART receiver when BRR[3:0] is different from 0000 OVER8 bit = 0 OVER8 bit = 1 M bit ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1 3.33% 3.88% 3.03% 3.53% 1.82% 2.73% Note: The data specified in Table 86...
Page 589: Multiprocessor Communication
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.5.7 Multiprocessor communication It is possible to perform multiprocessor communication with the USART (with several USARTs connected in a network). For instance one of the USARTs can be the master, its TX output connected to the RX inputs of the other USARTs. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master.
Page 590: Modbus Communication
Universal synchronous asynchronous receiver transmitter (USART) RM0091 4-bit/7-bit address mark detection (WAKE=1) In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are considered as data. In an address byte, the address of the targeted receiver is put in the 4 or 7 LSBs.
Page 591: Parity Control
RM0091 Universal synchronous asynchronous receiver transmitter (USART) to a timeout of 2 character times (for example 22 x bit time) must be programmed in the RTO register. When the receive line is idle for this duration, after the last stop bit is received, an interrupt is generated, informing the software that the current block reception is completed.
Page 592: Lin (Local Interconnection Network) Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0091 Parity generation in transmission If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected (PS=0) or an odd number of “1s”...
Page 593: Figure 237. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Figure 237. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBDF is not set Break Frame RX line Capture Strobe Break State machine Idle...
Page 594: Usart Synchronous Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0091 Figure 238. Break detection in LIN mode vs. Framing error detection In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data) Case 1: break occurring after an Idle RX line data 1 IDLE BREAK...
Page 595: Figure 239. Usart Example Of Synchronous Transmission
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Figure 239. USART example of synchronous transmission Data out Data in USART Synchronous device (e.g. slave SPI) SCLK Clock Figure 240. USART data clock timing diagram (M=0) Idle or next Idle or preceding Start Stop transmission...
Page 596: Single-Wire Half-Duplex Communication
Universal synchronous asynchronous receiver transmitter (USART) RM0091 Figure 241. USART data clock timing diagram (M=1) Idle or preceding Start transmission M=1 (9 data bits) Idle or next Stop transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data on TX (from master) MSB Stop...
Page 597: Smartcard Mode
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Apart from this, the communication protocol is similar to normal USART mode. Any conflicts on the line must be managed by software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continues as soon as data is written in the data register while the TE bit is set.
Page 598 Universal synchronous asynchronous receiver transmitter (USART) RM0091 shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. ● In transmission, if the Smartcard detects a parity error, it signals this condition to the USART by driving the line low (NACK).
Page 599: Figure 244. Parity Error Detection Using The 1.5 Stop Bits
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Figure 244 details how the NACK signal is sampled by the USART. In this example the USART is transmitting data and is configured with 1.5 stop bits. The receiver part of the USART is enabled in order to check the integrity of the data and the NACK signal. Figure 244.
Page 600 Universal synchronous asynchronous receiver transmitter (USART) RM0091 A block length counter is used to count all the characters received by the USART. This counter is reset when the USART is transmitting (TXE=0). The length of the block is communicated by the Smartcard in the third byte of the block (prologue field). This value must be programmed to the BLEN field in the USART_RTOR register.
Page 601: Irda Sir Endec Block
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Therefore, two methods are available for TS pattern recognition: Method 1: The USART is programmed in standard Smartcard mode/direct convention. In this case, the TS pattern reception generates a parity error interrupt and error signal to the card.
Page 602 Universal synchronous asynchronous receiver transmitter (USART) RM0091 encoded. While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. ● A 0 is transmitted as a high pulse and a 1 is transmitted as a 0. The width of the pulse is specified as 3/16th of the selected bit period in normal mode (see Figure 246).
Page 603: Figure 245. Irda Sir Endec- Block Diagram
RM0091 Universal synchronous asynchronous receiver transmitter (USART) IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally, this value is 1.8432 MHz (1.42 MHz <...
Page 604: Continuous Communication Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0091 25.5.15 Continuous communication using DMA The USART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Note: Please refer to Section 25.4: USART implementation on page 573 to determine if the DMA mode is supported.
Page 605: Figure 247. Transmission Using Dma
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Figure 247. Transmission using DMA Idle preamble Frame 1 Frame 2 Frame 3 TX line set by hardware set by hardware cleared by DMA read cleared by DMA read set by hardware TXE flag ignored by the DMA DMA request because DMA transfer is complete...
Page 606: Hardware Flow Control And Rs485 Driver Enable
Universal synchronous asynchronous receiver transmitter (USART) RM0091 Figure 248. Reception using DMA Frame 1 Frame 2 Frame 3 TX line set by hardware cleared by DMA read RXNE flag DMA request USART_DR DMA reads USART_DR cleared DMA TCIF flag set by hardware by software (Transfer complete) software configures the...
Page 607: Figure 250. Rts Flow Control
RM0091 Universal synchronous asynchronous receiver transmitter (USART) RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.
Page 608: Wakeup From Stop Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0091 RS485 Driver Enable The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register. This allows the user to activate the external transceiver control, through the DE (Driver Enable) signal. The assertion time is the time between the activation of the DE signal and the beginning of the START bit.
Page 609: Usart Interrupts
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.6 USART interrupts Table 89. USART interrupt requests Enable Interrupt event Event flag Control bit Transmit data register empty TXEIE CTS interrupt CTSIF CTSIE Transmission Complete TCIE Receive data register not empty (data ready to be read) RXNE RXNEIE Overrun error detected...
Page 610: Figure 252. Usart Interrupt Mapping Diagram
Universal synchronous asynchronous receiver transmitter (USART) RM0091 Figure 252. USART interrupt mapping diagram TCIE TXEIE CTSIF CTSIE IDLE IDLEIE USART RXNEIE interrupt RXNEIE RXNE PEIE LBDF LBDIE CMIE RTOF RTOIE EOBF EOBIE WUFIE MS19820V1 610/742 Doc ID 018940 Rev 1...
Page 611: Usart Registers
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.7 USART registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. 25.7.1 Control register 1 (USART_CR1) Address offset: 0x00 Reset value: 0x0000 EOBIE RTOIE DEAT[4:0] DEDT[4:0] OVER RXNEI...
Page 612 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Bit 15 OVER8: Oversampling mode 0: Oversampling by 16 1: Oversampling by 8 Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. This bit can only be written when the USART is disabled (UE=0). Bit 14 CMIE: Character match interrupt enable This bit is set and cleared by software.
Page 613 RM0091 Universal synchronous asynchronous receiver transmitter (USART) Bit 6 TCIE: Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever TC=1 in the USART_ISR register Bit 5 RXNEIE: RXNE interrupt enable This bit is set and cleared by software.
Page 614: Control Register 2 (Usart_Cr2)
Universal synchronous asynchronous receiver transmitter (USART) RM0091 25.7.2 Control register 2 (USART_CR2) Address offset: 0x04 Reset value: 0x0000 ABRE MSBFI DATAI RTOE ADD[7:4] ADD[3:0] ABRMOD[1:0] TXINV RXINV CLKE ADDM SWAP LINEN STOP[1:0] CPOL CPHA LBCL LBDIE LBDL Bits 31:28 ADD[7:4]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized.
Page 615 RM0091 Universal synchronous asynchronous receiver transmitter (USART) Bit 20 ABREN: Auto baud rate enable This bit is set and cleared by software. 0: Auto baud rate detection is disabled. 1: Auto baud rate detection is enabled. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’.
Page 616 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Bits 13:12 STOP[1:0]: STOP bits These bits are used for programming the stop bits. 00: 1 stop bit 01: Reserved. 10: 2 stop bits 11: 1.5 stop bit This bit field can only be written when the USART is disabled (UE=0). Bit 11 CLKEN: Clock enable This bit allows the user to enable the SCLK pin.
Page 617 RM0091 Universal synchronous asynchronous receiver transmitter (USART) Bit 5 LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. 0: 10-bit break detection 1: 11-bit break detection This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’.
Page 618: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0091 25.7.3 Control register 3 (USART_CR3) Address offset: 0x08 Reset value: 0x0000 WUFIE WUS[2:0] SCARCNT2:0] DDRE CTSIE CTSE RTSE DMAT DMAR SCEN NACK IRLP IREN Bits 31:23 Reserved, must be kept at reset value. Bit 22 WUFIE: Wakeup from Stop mode interrupt enable This bit is set and cleared by software.
Page 619 RM0091 Universal synchronous asynchronous receiver transmitter (USART) Bit 15 DEP: Driver enable polarity selection 0: DE signal is active high. 1: DE signal is active low. Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared.
Page 620 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping.
Page 621: Baud Rate Register (Usart_Brr)
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Bit 2 IRLP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes 0: Normal mode 1: Low-power mode This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and forced by hardware to ‘0’.
Page 622: Guard Time And Prescaler Register (Usart_Gtpr)
Universal synchronous asynchronous receiver transmitter (USART) RM0091 25.7.5 Guard time and prescaler register (USART_GTPR) Address offset: 0x10 Reset value: 0x0000 GT[7:0] PSC[7:0] Bits 31:16 Reserved, must be kept at reset value Bits 15:8 GT[7:0]: Guard time value This bit-field is used to program the Guard time value in terms of number of baud clock periods.
Page 623: Receiver Timeout Register (Usart_Rtor)
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.7.6 Receiver timeout register (USART_RTOR) Address offset: 0x14 Reset value: 0x0000 BLEN[7:0] RTO[23:16] RTO[15:0] Bits 31:24 BLEN[7:0]: Block Length This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1.
Page 624: Request Register (Usart_Rqr)
Universal synchronous asynchronous receiver transmitter (USART) RM0091 25.7.7 Request register (USART_RQR) Address offset: 0x18 Reset value: 0x0000 ABRR TXFRQ RXFRQ MMRQ SBKRQ w_r0 w_r0 w_r0 w_r0 w_r0 Bits 31:5 Reserved, must be kept at reset value Bit 4 TXFRQ: Transmit data flush request Writing 1 to this bit sets the TXE flag.
Page 625: Interrupt & Status Register (Usart_Isr)
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.7.8 Interrupt & status register (USART_ISR) Address offset: 0x1C Reset value: 0x00C0 SBKF BUSY ABRF ABRE EOBF RTOF CTSIF LBDF RXNE IDLE Bits 31:23 Reserved, must be kept at reset value. Bit 22 REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART.
Page 626 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Bit 18 SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
Page 627 RM0091 Universal synchronous asynchronous receiver transmitter (USART) Bit 11 RTOF: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register.
Page 628 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Bit 6 TC: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register.
Page 629: Interrupt Flag Clear Register (Usart_Icr)
RM0091 Universal synchronous asynchronous receiver transmitter (USART) Bit 2 NF: Noise detected flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. 0: No noise is detected 1: Noise is detected Note: 1.
Page 630 Universal synchronous asynchronous receiver transmitter (USART) RM0091 Bit 12 EOBCF: End of timeout clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’.
Page 631: Receive Data Register (Usart_Rdr)
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.7.10 Receive data register (USART_RDR) Address offset: 0x24 Reset value: Undefined RDR[8:0] Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 228).
Page 632: Transmit Data Register (Usart_Tdr)
Universal synchronous asynchronous receiver transmitter (USART) RM0091 25.7.11 Transmit data register (USART_TDR) Address offset: 0x28 Reset value: Undefined TDR[8:0] Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 TDR[8:0]: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure...
Page 633: Usart Register Map
RM0091 Universal synchronous asynchronous receiver transmitter (USART) 25.7.12 USART register map The table below gives the USART register map and reset values. Table 90. USART register map and reset values Offset Register USART_CR1 0x00 Reset value STOP USART_CR2 ADD[7:4] ADD[3:0] 0x04 [1:0] Reset value...
Page 634: Serial Peripheral Interface / Inter-Ic Sound (Spi/I2S)
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) 26.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software.
Page 635: Spi Extended Features
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) 26.1.2 SPI extended features ● SPI TI mode support 26.1.3 I²S features ● Simplex communication (only transmitter or receiver) ● Master or slave operations ● 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) ●...
Page 636: Communications Between One Master And One Slave
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Figure 253. SPI block diagram Address and data bus Read FIFO CRC controller MOSI Shift register MISO CRCEN RXONLY CRCN EXT CPOL CRCL CPHA DS[0:3] FIFO Write Communication BIDIOE controller Baud rate BR[2:0] generator InternalNSS...
Page 637: Figure 254. Full-Duplex Single Master/ Single Slave Application
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) and the MISO pins. During SPI communication, data is shifted synchronously on the SCK clock edges provided by the master. The master transmits the data to be sent to the slave via the MOSI line and receives data from the slave via the MISO line. When the data frame transfer is complete (all the bits are shifted) the information between the master and slave is exchanged.
Page 638: Standard Multi-Slave Communication
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 used for the transfer between the shift registers of the master and slave. The remaining MISO and MOSI pins pair is not used for communication and can be used as standard GPIOs. ●...
Page 639: Slave Select (Nss) Pin Management
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 257. Master and three independent slaves MOSI MOSI shift register shift register MISO MISO SPI clock generator I/O 1 Slave 1 Master I/O 2 I/O 3 MOSI shift register MISO Slave 2 MOSI shift register MISO...
Page 640: Communication Formats
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Hardware or software slave select management can be set using the SSM bit in the SPIx_CR1 register: ● Software NSS management (SSM = 1): in this configuration, slave select information is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is free for other application uses.
Page 641: Figure 259. Data Clock Timing Diagram
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a high-level idle state. If the CPHA bit is set, the second edge on the SCK pin is the first MSBit capture strobe (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set).
Page 642: Initialize Spi
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Data frame format The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set from 4-bit up to 16-bit length and the setting applies for both transmission and reception.
Page 643: Data Transmission And Reception Procedures
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Note: Step not required in slave mode. Step not required in TI mode In any master receive-only mode (RXONLY=1 or BIDIMODE=1 & BIDIOE=0), the clocks start running immediately after the SPI is enabled. 26.3.7 Data transmission and reception procedures RXFIFO and TXFIFO...
Page 644 Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 In receive-only modes, half duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0, RXONLY=1) the master starts the sequence immediately when both SPI is enabled and receive-only mode is activated. The clock signal is provided by the master and it does not stop until either SPI or receive-only mode is disabled by the master.
Page 645: Figure 261. Packing Data In Fifo For Transmission And Reception
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) The correct disable procedure for certain receive only modes is: Disable receive only mode in the specific time window while the last data frame is ongoing (RXONLY=0 or BIDIOE = 1) Wait until BSY=0 (the last data frame is processed). Read data until FRLVL[1:0] = 00 (read all the received data) Disable the SPI (SPE=0).
Page 646: Spi Status Flags
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Communication using DMA (direct memory addressing) To operate at its maximum speed and to facilitate the data register read/write process required to avoid overrun, the SPI features a DMA capability, which implements a simple request/acknowledge protocol.
Page 647: Spi Error Flags
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Rx buffer not empty (RXNE) The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register: ● If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or equal to 1/4 (8-bit).
Page 648: Spi Special Features
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 When an overrun condition occurs, the newly received value does not overwrite the previous one in the RXFIFO. The newly received value is discarded and all data transmitted subsequently is lost. Clearing the OVR bit is done by a read access to the SPI_DR register followed by a read access to the SPI_SR register.
Page 649: Ti Mode
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) consecutive data frame transfers when NSS stays at high level for the duration of one clock period at least. This mode allows the slave to latch data. NSSP pulse mode is designed for applications with a single master-slave pair.
Page 650: Crc Calculation
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Figure 263. TI mode transfer RELEASE DONTCARE MSBOUT LSBOUT MSBOUT LSBOUT MOSI 1 or 0 MSBIN LSBIN MSBIN LSBIN MISO FRAME 2 FRAME 1 MS19835V1 26.4.3 CRC calculation Two separate CRC calculators are implemented in order to check the reliability of transmitted and received data.
Page 651 RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) CRC transfer managed by CPU Communication starts and continues normally until the last data frame has to been sent or received in the SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1 register to indicate that the CRC frame transaction follows after the transaction of the currently processed data frame.
Page 652: Spi Interrupts
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Note: When the SPI is in slave mode, the CRC calculator is sensitive to the SCK slave input clock as soon as the CRCEN bit is set, and this is the case whatever the value of the SPE bit. In order to avoid any wrong CRC calculation, the software must enable CRC calculation only when the clock is stable (in steady state).
Page 653: Figure 264. I 2 S Block Diagram
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 264. I S block diagram Address and data bus Tx buffer BSY OVR MODF CRC TxE RxNE SIDE 16-bit MOSI/ SD Shift register MISO LSB first Communication 16-bit control Rx buffer NSS/WS I2SCFG I2SSTD...
Page 654: Supported Audio Protocols
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 An additional pin can be used when a master clock output is needed for some external audio devices: ● MCK: Master Clock (mapped separately) is used, when the I S is configured in master mode (and when the MCKOE bit in the SPIx_I2SPR register is set), to output this additional clock generated at a preconfigured frequency rate equal to 256 ×...
Page 655: Figure 265. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 265. I S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) Transmission Reception May be 16-bit or 32-bit Channel left Channel right MS19591V1 Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver).
Page 656: Figure 268. Receiving 0X8Eaa33
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Figure 268. Receiving 0x8EAA33 First read to Data register Second read to Data register 0x8EAA 0x33XX Only the 8 MSB are sent to compare the 24 bits 8 LSBs have no meaning and can be anything MS19594V1 Figure 269.
Page 657: Figure 271. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length With Cpol = 0
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) MSB justified standard For this standard, the WS signal is generated at the same time as the first data bit, which is the MSBit. Figure 271. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 Transmission Reception 16- or 32 bit data...
Page 658: Figure 274. Lsb Justified 16-Bit Or 32-Bit Full-Accuracy With Cpol = 0
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats). Figure 274. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 Transmission Reception 16- or 32-bit data...
Page 659: Figure 277. Operations Required To Receive 0X3478Ae
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 277. Operations required to receive 0x3478AE First read from Data register Second read from Data register conditioned by RXNE=1 conditioned by RXNE=1 0xXX34 0x78AE Only the 8 LSB of the half-word are significant. A field of 0x00 is forced instead of the 8 MSBs.
Page 660: Clock Generator
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 PCM standard For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPIx_I2SCFGR register. Figure 280.
Page 661: Figure 282. Audio Sampling Frequency Definition
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 282. Audio sampling frequency definition 16-or 32-bit 16-or 32-bit left channel right channel 32- or 64-bits sampling point sampling point : audio sampling frequency MS30108V1 When the master mode is configured, a specific action needs to be taken to properly program the linear divider in order to communicate with the desired audio frequency.
Page 662: Table 92. Audio-Frequency Precision Using Standard 8 Mhz Hse
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Table 92. Audio-frequency precision using standard 8 MHz HSE SYSCLK Data Target fs I2SDIV I2SODD MCLK Real fs (KHz) Error length (Hz) (MHz) 96000 93750 2.3438% 96000 93750 2.3438% 48000 48387.0968 0.8065% 48000 46875 2.3438%...
Page 663: I 2 S Master Mode
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) 26.6.4 S master mode The I S can be configured in master mode. This means that the serial clock is generated on the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not, controlled by the MCKOE bit in the SPIx_I2SPR register.
Page 664: I 2 S Slave Mode
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Reception sequence The operating mode is the same as for transmission mode except for the point 3 (refer to the procedure described in Section 26.6.4: I2S master mode), where the configuration should set the master reception mode through the I2SCFG[1:0] bits.
Page 665 RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) clock and WS signals are input from the external master connected to the I S interface. There is then no need, for the user, to configure the clock. The configuration steps to follow are listed below: Set the I2SMOD bit in the SPIx_I2SCFGR register to select I S mode and choose the S standard through the I2SSTD[1:0] bits, the data length through the DATLEN[1:0]...
Page 666 Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Transmission sequence The transmission sequence begins when the external master device sends the clock and when the NSS_WS signal requests the transfer of data. The slave has to be enabled before the external master starts the communication. The I S data register has to be loaded before the master initiates the communication.
Page 667: I 2 S Status Flags
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) For more details about the read operations depending the I S standard mode selected, refer Section 26.6.2: Supported audio protocols. If data are received while the preceding received data have not yet been read, an overrun is generated and the OVR flag is set.
Page 668: I 2 S Error Flags
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Channel Side flag (CHSIDE) In transmission mode, this flag is refreshed when TXE goes high. It indicates the channel side to which the data to transfer on SD has to belong. In case of an underrun error event in slave transmission mode, this flag is not reliable and I S needs to be switched off and switched on before resuming the communication.
Page 669: I 2 S Interrupts
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) can be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by software when the status register is read. 26.6.8 S interrupts Table 93 provides the list of I S interrupts.
Page 670: Spi And I 2 S Registers
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 26.7 SPI and I S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access. 26.7.1 SPI control register 1 (SPIx_CR1) Address offset: 0x00 Reset value: 0x0000 BIDI...
Page 671 RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Bit 9 SSM: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. 0: Software slave management disabled 1: Software slave management enabled Note: This bit is not used in I S mode and SPI TI mode Bit 8 SSI: Internal slave select...
Page 672: Spi Control Register 2 (Spix_Cr2)
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 26.7.2 SPI control register 2 (SPIx_CR2) Address offset: 0x04 Reset value: 0x0000 LDMA LDMA FRXT Res. DS [3:0] TXEIE RXNEIE ERRIE NSSP SSOE TXDMAEN RXDMAEN Bit 15 Reserved, must be kept at reset value. Bit 14 LDMA_TX: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even.
Page 673 RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Bit 11:8 DS [3:0]: Data size These bits configure the data length for SPI transfers: 0000: Not used 0001: Not used 0010: Not used 0011: 4-bit 0100: 5-bit 0101: 6-bit 0110: 7-bit 0111: 8-bit 1000: 9-bit 1001: 10-bit...
Page 674: Spi Status Register (Spix_Sr)
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment.
Page 675 RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Bit 7 BSY: Busy flag 0: SPI (or I2S) not busy 1: SPI (or I2S) is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to Section 26.3.8: SPI Status flags Procedure for disabling the SPI on page...
Page 676: Spi Data Register (Spix_Dr)
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 26.7.4 SPI data register (SPIx_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 26.3.7: Data transmission and reception...
Page 677: Spi Rx Crc Register (Spix_Rxcrcr)
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) 26.7.6 SPI Rx CRC register (SPIx_RXCRCR) Address offset: 0x14 Reset value: 0x0000 RxCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes.
Page 678: Spix_I 2 S Configuration Register (Spix_I2Scfgr)
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 26.7.8 SPIx_I S configuration register (SPIx_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 PCMSY Res. Res. Res. Res. I2SMOD I2SE I2SCFG Res. I2SSTD CKPOL DATLEN CHLEN Bits 15:12 Reserved: Forced to 0 by hardware Bit 11 I2SMOD: I2S mode selection 0: SPI mode is selected 1: I2S mode is selected...
Page 679: Spix_I 2 S Prescaler Register (Spix_I2Spr)
RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S) Bits 2:1 DATLEN: Data length to be transferred 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: Not allowed Note: For correct operation, these bits should be configured when the I S is disabled.
Page 680: Spi/I2S Register Map
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091 26.7.10 SPI/I2S register map Table 94 shows the SPI/I2S register map and reset values. Table 94. SPI register map and reset values Offset Register SPIx_CR1 BR [2:0] 0x00 Reset value SPIx_CR2 DS[3:0] 0x04 Reset value SPIx_SR...
Page 681: Touch Sensing Controller (Tsc)
RM0091 Touch sensing controller (TSC) Touch sensing controller (TSC) 27.1 Introduction The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...).
Page 682: Tsc Functional Description
Touch sensing controller (TSC) RM0091 27.3 TSC functional description 27.3.1 TSC block diagram The block diagram of the touch sensing controller is shown in Figure 284: TSC block diagram. Figure 284. TSC block diagram SYNC Pulse generator G1_IO1 HCLK Clock G1_IO2 prescalers G1_IO3...
Page 683: Figure 285. Surface Charge Transfer Analog I/O Group Structure
RM0091 Touch sensing controller (TSC) The remaining GPIOs are dedicated to the electrodes and are commonly called channels. For some specific needs (such as proximity detection), it is be possible to simultaneously enable more than one channel per analog I/O group. Figure 285.
Page 684: Reset And Clocks
Touch sensing controller (TSC) RM0091 Table 95. Acquisition sequence summary G1_IO1 G1_IO2 G1_IO3 G1_IO4 State State description (electrode) (sampling) (electrode) (electrode) Output open- Input floating drain low with Input floating with analog switch Discharge all C with analog analog switch closed switch closed closed...
Page 685: Charge Transfer Acquisition Sequence
RM0091 Touch sensing controller (TSC) 27.3.4 Charge transfer acquisition sequence An example of a charge transfer acquisition sequence is detailed in Figure 287. Figure 287. Charge transfer acquisition sequence charge transfer frequency CLK_AHB Pulse low state Discharge Pulse high state State (charge transfer and C...
Page 686: Spread Spectrum Feature
Touch sensing controller (TSC) RM0091 27.3.5 Spread spectrum feature The spread spectrum feature allows to generate a variation of the charge transfer frequency. This is done to improve the robustness of the charge transfer acquisition in noisy environments and also to reduce the induced emission. The maximum frequency variation is in the range of 10 % to 50 % of the nominal charge transfer period.
Page 687: Sampling Capacitor I/O And Channel I/O Mode Selection
RM0091 Touch sensing controller (TSC) 27.3.7 Sampling capacitor I/O and channel I/O mode selection To allow the GPIOs to be controlled by the touch sensing controller, the corresponding alternate function must be enabled through the standard GPIO registers and the GPIOxAFR registers.
Page 688: Acquisition Mode
Touch sensing controller (TSC) RM0091 27.3.8 Acquisition mode The touch sensing controller offers two acquisition modes: ● Normal acquisition mode: the acquisition starts as soon as the START bit in the TSC_CR register is set. ● Synchronized acquisition mode: the acquisition is enabled by setting the START bit in the TSC_CR register but only starts upon the detection of a falling edge or a rising edge and high level on the SYNC input pin.
Page 689: Capacitive Sensing Gpios
RM0091 Touch sensing controller (TSC) 27.3.10 Capacitive sensing GPIOs The table below provides an overview of the capacitive sensing GPIOs available on STM32F05xxx devices. Table 98. Capacitive sensing GPIOs available on STM32F05xxx devices Capacitive sensing Capacitive sensing Pin name Pin name group name group name G1_IO1...
Page 690: Tsc Registers
Touch sensing controller (TSC) RM0091 27.6 TSC registers Refer to Section 1.1 on page 34 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 27.6.1 TSC control register (TSC_CR) Address offset: 0x00 Reset value: 0x0000 0000 CTPH[3:0]...
Page 691 RM0091 Touch sensing controller (TSC) Bit 15 SSPSC: Spread spectrum prescaler This bit is set and cleared by software. It selects the AHB clock divider used to generate the spread spectrum clock (f SSCLK 0: f HCLK 1: f HCLK Note: This bit must not be modified when an acquisition is on-going.
Page 692 Touch sensing controller (TSC) RM0091 Bit 1 START: Start a new acquisition This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the acquisition is complete or by software to cancel the on-going acquisition. 0: Acquisition not started 1: Start a new acquisition Bit 0 TSCE: Touch sensing controller enable...
Page 693: Tsc Interrupt Enable Register (Tsc_Ier)
RM0091 Touch sensing controller (TSC) 27.6.2 TSC interrupt enable register (TSC_IER) Address offset: 0x04 Power-on reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 694: Tsc Interrupt Status Register (Tsc_Isr)
Touch sensing controller (TSC) RM0091 27.6.4 TSC interrupt status register (TSC_ISR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 695: Tsc I/O Analog Switch Control Register (Tsc_Ioascr)
RM0091 Touch sensing controller (TSC) 27.6.6 TSC I/O analog switch control register (TSC_IOASCR) Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:24 Reserved, must be kept at reset value.
Page 696: Tsc I/O Channel Control Register (Tsc_Ioccr)
Touch sensing controller (TSC) RM0091 27.6.8 TSC I/O channel control register (TSC_IOCCR) Address offset: 0x28 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:24 Reserved, must be kept at reset value.
Page 697: Tsc I/O Group X Counter Register (Tsc_Iogxcr) (X=1
RM0091 Touch sensing controller (TSC) Bits 5:0 GxE: Analog I/O group x enable These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. 0: Acquisition on analog I/O group x disabled 1: Acquisition on analog I/O group x enabled 27.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x=1..6)
Page 698 Touch sensing controller (TSC) RM0091 Table 101. TSC register map and reset values (continued) Offset Register TSC_IOSCR 0x0020 Reset value 0x0024 Reserved TSC_IOCCR 0x0028 Reset value 0x002C Reserved TSC_IOGCSR 0x0030 Reset value TSC_IOG1CR CNT[13:0] 0x0034 Reset value TSC_IOG2CR CNT[13:0] 0x0038 Reset value TSC_IOG3CR CNT[13:0]...
Page 699: Hdmi-Cec Controller (Hdmi-Cec)
RM0091 HDMI-CEC controller (HDMI-CEC) HDMI-CEC controller (HDMI-CEC) 28.1 Introduction Consumer Electronics Control (CEC) is part of HDMI (High-Definition Multimedia Interface) standard as appendix supplement 1. It consists of a protocol that provides high-level control functions between all of the various audiovisual products in a user environment.
Page 700: Hdmi-Cec Functional Description
HDMI-CEC controller (HDMI-CEC) RM0091 28.3 HDMI-CEC functional description 28.3.1 HDMI-CEC pin The CEC bus consists of a single bidirectional line that is used to transfer data in and out of the device. It is connected to a +3.3 V supply voltage via a 27 kΩ pull-up resistor. The output stage of the device must have an open-drain or open-collector to allow a wired-and connection.
Page 701: Message Description
RM0091 HDMI-CEC controller (HDMI-CEC) 28.3.2 Message description All transactions on the CEC line consist of an initiator and one or more followers. The initiator is responsible for sending the message structure and the data. The follower is the recipient of any data and is responsible for setting any acknowledgement bits. A message is conveyed in a single frame which consists of a start bit followed by a header block and optionally an opcode and a variable number of operand blocks.
Page 702: Arbitration
HDMI-CEC controller (HDMI-CEC) RM0091 Figure 292. Bit timings 4.5ms +/-0.2ms START BIT 3.7ms +/-0.2ms high impedance low impedance 2.4ms +/-0.35ms DATA BIT INITIATOR LOGICAL 0 1.5ms +/-0.2ms high impedance low impedance DATA BIT 2.4ms +/-0.35ms INITIATOR LOGICAL 1 0.6ms +/-0.2ms high impedance low impedance 2.4ms +/-0.35ms...
Page 703: Sft Option Bit
RM0091 HDMI-CEC controller (HDMI-CEC) Figure 295 shows an example for a SFT of three nominal bit periods Figure 295. SFT of three nominal bit periods last bit of previous frame Start bit A configurable time window is counted before starting the transmission. In the SFT=0x0 configuration the HDMI-CEC device performs automatic SFT calculation ensuring compliancy to the HDMI-CEC Standard: ●...
Page 704: Error Handling
HDMI-CEC controller (HDMI-CEC) RM0091 SFTOPT=1 bus-event condition starting the SFT timer is detected in the following cases: ● In case of a regular end of transmission/reception, when TXEND/RXEND bits are set at the minimum nominal data bit duration of the last bit in the message (ACK bit). ●...
Page 705: Short Bit Period Error (Sbpe)
RM0091 HDMI-CEC controller (HDMI-CEC) When BRE is detected in a broadcast message with BRESTP=1 an error bit is generated even if BREGEN=0 to enforce initiator’s retry of the failed transmission. Error bit generation can be disabled by configuring BREGEN=0, BRDNOGEN=1. 28.5.4 Short Bit Period Error (SBPE) SBPE is set when a bit falling edge is detected earlier than expected (see...
Page 706: Table 103. Error Handling Timing Parameters
HDMI-CEC controller (HDMI-CEC) RM0091 Table 103. Error handling timing parameters Time RXTOL Description Bit start event. The earliest time for a low - high transition when indicating a logical 1. The nominal time for a low - high transition when indicating a logical 1.
Page 707: Transmission Error Detection (Txerr)
RM0091 HDMI-CEC controller (HDMI-CEC) 28.5.6 Transmission Error Detection (TXERR) The CEC initiator sets the TXERR flag if detecting low impedance on the CEC line when it is transmitting high impedance and is not expecting a follower asserted bit. TXERR flag also generates a CEC interrupt if the TXERRIE=1.
Page 708: Hdmi-Cec Interrupts
HDMI-CEC controller (HDMI-CEC) RM0091 Table 104. TXERR timing parameters (continued) Time RXTOL Description The nominal time a device is permitted return to a high impedance state (logical 0). The latest time a device is permitted return to a high impedance state (logical 0). 1.85 The earliest time for the start of a following bit.
Page 709: Hdmi-Cec Registers
RM0091 HDMI-CEC controller (HDMI-CEC) 28.7 HDMI-CEC registers Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions. 28.7.1 CEC control register (CEC_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res.
Page 710 HDMI-CEC controller (HDMI-CEC) RM0091 Bit 0 CECEN: CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECON=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. 0: CEC peripheral is off 1: CEC peripheral is on 710/742...
Page 711: Cec Configuration Register (Cec_Cfgr)
RM0091 HDMI-CEC controller (HDMI-CEC) 28.7.2 CEC configuration register (CEC_CFGR) This register is used to configure the HDMI-CEC controller. Address offset: 0x04 Reset value: 0x0000 0000 Caution: It is mandatory to write CEC_CFGR only when CECEN=0 LSTN OAR[14:0] LBPE BRDN Res. Res.
Page 712 HDMI-CEC controller (HDMI-CEC) RM0091 Bit 6 LBPEGEN: Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. 0: LBPE detection does not generate an Error-Bit on the CEC line 1: LBPE detection generates an Error-Bit on the CEC line Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0 Bit 5 BREGEN: Generate Error-Bit on Bit Rising Error...
Page 713: Cec Tx Data Register (Cec_Txdr)
RM0091 HDMI-CEC controller (HDMI-CEC) 28.7.3 CEC Tx data register (CEC_TXDR) Address offset: 0x8 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 714 HDMI-CEC controller (HDMI-CEC) RM0091 Bit 12 TXACKE: Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls.
Page 715: Cec Interrupt Enable Register (Cec_Ier)
RM0091 HDMI-CEC controller (HDMI-CEC) Bit 3 BRE: Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing.
Page 716 HDMI-CEC controller (HDMI-CEC) RM0091 Bit 9 TXENDIE: Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software. 0: TXEND interrupt disabled 1: TXEND interrupt enabled Bit 8 TXBRIE: Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software. 0: TXBR interrupt disabled 1: TXBR interrupt enabled Bit 7 ARBLSTIE: Arbitration Lost Interrupt Enable...
Page 717: Hdmi-Cec Register Map
RM0091 HDMI-CEC controller (HDMI-CEC) 28.7.7 HDMI-CEC register map The following table summarizes the HDMI-CEC registers. Table 106. HDMI-CEC register map and reset values Offset Register CEC_CR 0x00 Reset value CEC_CFGR OAR[14:0] SFT[2:0] 0x04 Reset value CEC_TXDR TXD[7:0] 0x08 Reset value CEC_RXDR RXD[7:0] 0x0C...
Page 718: Debug Support (Dbg)
Debug support (DBG) RM0091 Debug support (DBG) This section applies to the whole STM32F05xxx family, unless otherwise specified. 29.1 Overview The STM32F05xxx devices are built around a Cortex-M0 core which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint).
Page 719: Reference Arm Documentation
RM0091 Debug support (DBG) The ARM Cortex-M0 core provides integrated on-chip debug support. It is comprised of: ● SW-DP: Serial wire ● BPU: Break point unit ● DWT: Data watchpoint trigger It also includes debug features dedicated to the STM32F05xxx: ●...
Page 720: Sw Debug Port Pins
Debug support (DBG) RM0091 29.3.1 SW debug port pins Two pins are used as outputs for the SW-DP as alternate functions of general purpose I/Os. These pins are available on all packages. Table 107. SW debug port pins SW debug port SW-DP pin name assignment Type...
Page 721: Mcu Device Id Code
RM0091 Debug support (DBG) 29.4.1 MCU device ID code The STM32F051x6 and STM32F051x8 integrate an MCU ID code. This ID identifies the ST MCU part number and the die revision. This code is accessible by the software debug port (two pins) or by the user software. DBGMCU_IDCODE Address: 0x40015800 Only 32-bits access supported.
Page 722: Sw Protocol Sequence
Debug support (DBG) RM0091 29.5.2 SW protocol sequence Each sequence consist of three phases: Packet request (8 bits) transmitted by the host Acknowledge response (3 bits) transmitted by the target Data transfer phase (33 bits) transmitted by the host or the target Table 108.
Page 723: Sw-Dp State Machine (Reset, Idle States, Id Code)
RM0091 Debug support (DBG) 29.5.3 SW-DP state machine (reset, idle states, ID code) The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It follows the JEP-106 standard. This ID code is the default ARM one and is set to 0x1BA01477 (corresponding to Cortex-M0).
Page 724 Debug support (DBG) RM0091 Table 111. SW-DP registers (continued) CTRLSEL bit A(3:2) of SELECT Register Notes register Purpose is to: – request a system or debug power-up – configure the transfer operation for AP accesses Read/Write DP-CTRL/STAT – control the pushed compare and pushed verify operations.
Page 725: Sw-Ap Registers
RM0091 Debug support (DBG) 29.5.6 SW-AP registers Access to these registers are initiated when APnDP=1 There are many AP Registers addressed as the combination of: ● The shifted value A[3:2] ● The current value of the DP SELECT register. Table 112. 32-bit debug port registers addressed through the shifted value A[3:2] Address A(3:2) value Description Reserved, must be kept at reset value.
Page 726: Bpu (Break Point Unit)
Debug support (DBG) RM0091 These registers are not reset by a system reset. They are only reset by a power-on reset. Refer to the Cortex-M0 TRM for further details. To Halt on reset, it is necessary to: ● enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control Register ●...
Page 727: Debug Support For Low-Power Modes
RM0091 Debug support (DBG) 29.9.1 Debug support for low-power modes To enter low-power mode, the instruction WFI or WFE must be executed. The MCU implements several low-power modes which can either deactivate the CPU clock or reduce the power of the CPU. The core does not allow FCLK or HCLK to be turned off during a debug session.
Page 728: Debug Mcu Configuration Register (Dbgmcu_Cr)
Debug support (DBG) RM0091 29.9.3 Debug MCU configuration register (DBGMCU_CR This register allows the configuration of the MCU under DEBUG. This concerns: ● Low-power mode support This DBGMCU_CR is mapped at address 0x4001 5804. It is asynchronously reset by the PORESET (and not the system reset). It can be written by the debugger under system reset.
Page 729: Debug Mcu Apb Low Freeze Register (Dbgmcu_Apb1_Fz)
RM0091 Debug support (DBG) 29.9.4 Debug MCU APB low freeze register (DBGMCU_APB1_FZ) The DBGMCU_APB1_FZ register is used to configure the MCU under DEBUG. It concerns some APB peripherals: ● Timer clock counter freeze ● I2C SMBUS timeout freeze ● Window watchdog and independent watchdog counter freeze support This DBGMCU_APB1_FZ is mapped at address 0x4001 5808.
Page 730 Debug support (DBG) RM0091 Bit 9 Reserved, must be kept at reset value. Bit 8 DBG_TIM14_STOP: TIM14 counter stopped when core is halted 0: The counter clock of TIM14 is fed even if the core is halted 1: The counter clock of TIM14 is stopped when the core is halted Bits 7:5 Reserved, must be kept at reset value.
Page 731: Debug Mcu Apb2 Freeze Register (Dbgmcu_Apb2_Fz)
RM0091 Debug support (DBG) 29.9.5 Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) The DBGMCU_APB2_FZ register is used to configure the MCU under DEBUG. It concerns some APB peripherals: ● Timer clock counter freeze This register is mapped at address 0x4001580C. It is asynchronously reset by the POR (and not the system reset). It can be written by the debugger under system reset.
Page 732: Dbg Register Map
Debug support (DBG) RM0091 29.10 DBG register map The following table summarizes the Debug registers. Table 114. DBG register map and reset values Addr. Register DBGMCU_ REV_ID DEV_ID IDCODE Reset value X X X X X X X X X X X X X X X X X X X X X X X X X X X X DBGMCU_CR Reset value...
Page 733: Device Electronic Signature
RM0091 Device electronic signature Device electronic signature The device electronic signature is stored in the System memory area of the Flash memory module, and can be read using the debug interface or by the CPU. It contains factory- programmed identification and calibration data that allow the user firmware or other external devices to automatically match to the characteristics of the STM32F05xxx microcontroller.
Page 734 Device electronic signature RM0091 Address offset: 0x04 Read only = 0xXXXX XXXX where X is factory-programmed UID[63:48] UID[47:32] Bits 31:8 UID[63:40]: LOT_NUM[23:0] Lot number (ASCII encoded) Bits 7:0 UID[39:32]: WAF_NUM[7:0] Wafer number (8-bit unsigned number) Address offset: 0x08 Read only = 0xXXXX XXXX where X is factory-programmed UID[95:80] UID[79:64] Bits 31:0 UID[95:64]: LOT_NUM[55:24]...
Page 735: Memory Size Data Register
RM0091 Device electronic signature 30.2 Memory size data register 30.2.1 Flash size data register Base address: 0x1FFF F7CC Address offset: 0x00 Read only = 0xXXXX where X is factory-programmed FLASH_SIZE Bits 15:0 FLASH_SIZE[15:0]: Flash memory size This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
Page 736 Index RM0091 Index ADC_CCR ......202 ADC_CFGR1 ......196 ADC_CFGR2 .
Page 737 RM0091 Index EXTI_EMR ......163 EXTI_FTSR ......164 EXTI_IMR .
Page 738 Index RM0091 RCC_AHBENR ..... . .102 RCC_AHBRSTR ..... .112 RCC_APB1ENR .
Page 739 RM0091 Index TIM15_ARR ......415 TIM15_BDTR ......417 TIM15_CCER .
Page 740 Index RM0091 TSC_IOCCR1 ......696 TSC_IOGCSR ......696 TSC_IOGxCR .
Page 741: Revision History
RM0091 Revision history Revision history Table 115. Document revision history Date Revision Changes 06-Apr-2012 Initial release Doc ID 018940 Rev 1 741/742...
Page 742 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.