Dspi Dsi Serialization Data Register 1 (Dspi_Sdr1) - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
Field
Mask
0–31
0 The bit in the received DSI frame does not produce a DDI interrupt.
MASK 1 The bit in the received DSI frame produces a DDI interrupt if the data bit matches the configured
polarity.
46.3.20 DSPI DSI Deserialized Data Polarity Interrupt Register 0 (DSPI_DPIR0)
DPIR0 defines which data bit value in the 32 LSB of received DSI frame generates the DDI
interrupt.
When DSICR1[DSI64E] is set, DPIR1 is the MSB half and DPIR0 is the LSB half of the 64-
bit DPIR.
Address: Base + 0x00EC
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 603. DSPI DSI Deserialized Data Polarity Interrupt Register 0 (DSPI_DPIR0)
Field
Data Polarity
0–31
0 If the received bit is 0, the SR[DDIF] bit is set.
DP
1 If the received bit is 1, the SR[DDIF] bit is set.
46.3.21

DSPI DSI Serialization Data Register 1 (DSPI_SDR1)

Read-only SDR1 contains the states of the 32 MSB parallel input signals.
The states of these signals are latched into the SDR1 on the rising edge of every protocol
clock.
When DSICR0[TXSS] is cleared, the data in SDR1 and SDR0 is the source of the DSI
frames.
The concatenation of {DSPI_SDR1, DSPI_SDR0} provides the 64-bit data to be serialized.
This register is valid only when DSICR1[DSI64E] is set.
1172/2058
Table 631. DSPI_DIMR0 field descriptions
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0
Table 632. DSPI_DPIR0 field descriptions
DocID027809 Rev 4
Description
6 7 8 9
DP
0 0 0 0
22 23 24 25
DP
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
RM0400
14 15
0 0
30 31
0 0