Table 325. Test Mode Disable Block Select - STMicroelectronics SPC572L series Reference Manual

Embedded Flash Memory (MP55)
overall protection is obtained in conjunction with sidebands: UTEST and BAF have
dedicated program protection sidebands (SoC specific).
29.4.6.2 Test mode disable
In the TestFlash area a mechanism is also available to disable entry into Test mode.
Extreme care must be taken when using this feature, as blocks that are selected for
protection in this way cannot be analyzed for possible failures by manufacture failure
analysts.
Protection of this sort prevents all high voltage operations to the flash executed by the
internal FPEC as well as reads from FPEC, including Array Integrity Check or Margin Read,
when using Test mode interfaces. Protection through other interfaces is managed through
normal User mode protection mechanisms, that are SoC specific.
To disable manufacturer entry into Test mode, first program the Test Mode Disable Seal
location to 0x5A4B_3C2D and once the next reset is asserted, Test mode is disabled.
It is possible to create a password to enable manufacturer entry into Test mode. This can be
programmed into the Test Mode Disable Override Passcode. It is safest to do this prior to
censoring the part to avoid unintended lockout. The passcode may not be 0x0000_0000,
0xFFFF_FFFF, or 0x5555_5555. These are all invalid passcodes and are not accepted for
override. If the customer desires that override never be possible, one of the three invalid
passcodes should be put into this location. Passcodes may be entered to authenticate entry
(if enabled) by performing a register Write to address 0x0x90.
Only blocks selected in the Test Mode Disable Block Select field are controlled by the Test
Mode Disable feature. Thus is it possible for customers to select blocks for this type of
protection, and render them ineligible for manufacturer failure analysis. Bits programmed to
'0' in the Test Mode Disable Block Select field designate blocks that are controlled by Test
Mode Disable feature. The TestFlash block, and thus the UTEST and BAF sections, is
always protected once the Test Mode Disable Seal password is written. In order to permit
two opportunities to select blocks for Test Mode disable, two regions are available: one at
address 0x804010, and the other at address 0x804030; both 128-bit sized (only 80 may be
effective, depending on actual sectorization). The bits of these two regions are logically
ANDed in order to define which blocks are effectively selected for the Test Mode Disable
feature.
The 80-bit Block Select field is organized as follows, and aligned in the way blocks are
defined in the LOCK registers:
644/2058

Table 325. Test Mode Disable block select

Block
Blocks in Mid space
Blocks in Low space
Blocks in High space
Blocks in 256K space
DocID027809 Rev 4
Block selection bits
Data[15:0]
Data[29:16]
Data[47:32]
Data[78:48]
RM0400