Introduction - STMicroelectronics SPC572L series Reference Manual

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Debug and Calibration Interface (DCI)
58
Debug and Calibration Interface (DCI)
58.1

Introduction

The Debug and Calibration Interface (DCI) module provides debug and calibration features
for the MCU. It includes a standard 1149.1/1149.7 compatible JTAG interface which is used
to connect with an external JTAG tool using a low frequency clock interface.
It also features a software based debug mode which can be controlled by the MCU without
using an external tool. Additionally, the DCI provides features for debug control using break-
points and synchronous restart of the cores. This chapter describes the DCI features for the
Production device (PD) only.
58.1.1
Features
The DCI features are the following:
Debug mode enable control for connected tool or software
1149.1 and 1149.7 controllers
Debug break and cross-triggering control
Synchronous restart control for CPU when exiting debug mode
Tool hot plug capability
Security access control
Debug reset control
58.1.2
Overview
The DCI can take the following different inputs for its JTAG signals:
P.JTAG—JTAG signals coming from the Production device JTAG pads. This is the
standard 5-pin JTAG interface and is the default operating mode.
M.JTAG—JTAG signals generated by JTAGM module using software debug mode.
By default the DCI operates in standard 5-pin JTAG mode (IEEE 1149.1). It can be
configured in 3-pin reduced pin JTAG mode (IEEE 1149.7) after starting from standard 5-pin
JTAG mode.
When reduced pin JTAG mode (IEEE 1149.7) is configured TMSC pin is configured in
bidirectional mode during operation.
The DCI also provides a centralized break control for system IPs and cores, which can be
controlled by an external tool as well as the internal debug peripherals such as GTM/SPU,
etc. The DCI also provides the Event Out (EVTO) signals to the debug tool in case of the
occurrence of any internal debug event.
Figure 1013
1720/2058
In software debug mode, there is no tool, and debug software running on the MCU
generates the JTAG packets and writes them to JTAGM using special debug
registers in the JTAGM module.
shows the DCI block diagram.
DocID027809 Rev 4
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