Figure 991. Dbcr4 Register - STMicroelectronics SPC572L series Reference Manual

RM0400
Bit Name
Data Value Compare 1 Byte Enables
Specifies which bytes in the aligned doubleword value associated with the memory access
are compared to the corresponding bytes in DVC1. Inactive byte lanes of a memory access
smaller than 64 bits are automatically masked by hardware. If all bits in the DVC1BE field are
clear, then a match will occur regardless of the data. Misaligned accesses that cross a
doubleword boundary are not fully supported.
1xxxxxxx
16:23 DVC1BE
x1xxxxxx
xx1xxxxx
xxx1xxxx
xxxx1xxx
xxxxx1xx
xxxxxx1x
xxxxxxx1
Data Value Compare2 Byte Enables
Specifies which bytes in the aligned doubleword value associated with the memory access
are compared to the corresponding bytes in DVC2. Inactive byte lanes of a memory access
smaller than 64 bits are automatically masked by hardware. If all bits in the DVC1BE field are
clear, then a match will occur regardless of the data. Misaligned accesses that cross a
doubleword boundary are not fully supported.
1xxxxxxx
24:31 DVC2BE
x1xxxxxx
xx1xxxxx
xxx1xxxx
xxxx1xxx
xxxxx1xx
xxxxxx1x
xxxxxxx1
57.3.2.4 Debug Control Register 4 (DBCR4)
Debug Control Register 4 is used to extend data address and value compare matching
functionality. DBCR4 is shown in
0 0
0 1 2 3 4 5 6
1. DBCR4 is reset by processor reset p_reset_b if EDBCR0
EDBRAC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by
EDBRAC0 will be reset by p_reset_b.
Table 942
Table 941. DBCR2 field descriptions (Continued)
Byte lane 0 is enabled for comparison with the value in bits 0:7 of DVC1.
Byte lane 1 is enabled for comparison with the value in bits 8:15 of DVC1.
Byte lane 2 is enabled for comparison with the value in bits 16:23 of DVC1.
Byte lane 3 is enabled for comparison with the value in bits 24:31 of DVC1.
Byte lane 4 is enabled for comparison with the value in bits 32:39 of DVC1.
Byte lane 5 is enabled for comparison with the value in bits 40:47 of DVC1.
Byte lane 6 is enabled for comparison with the value in bits 48:55 of DVC1.
Byte lane 7 is enabled for comparison with the value in bits 56:63 of DVC1.
Byte lane 0 is enabled for comparison with the value in bits 0:7 of DVC2.
Byte lane 1 is enabled for comparison with the value in bits 8:15 of DVC2.
Byte lane 2 is enabled for comparison with the value in bits 16:23 of DVC2.
Byte lane 3 is enabled for comparison with the value in bits 24:31 of DVC2.
Byte lane 4 is enabled for comparison with the value in bits 32:39 of DVC2.
Byte lane 5 is enabled for comparison with the value in bits 40:47 of DVC2.
Byte lane 6 is enabled for comparison with the value in bits 48:55 of DVC2.
Byte lane 7 is enabled for comparison with the value in bits 56:63 of DVC2.
0 0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 563; Read/Write; Reset

Figure 991. DBCR4 register

provides bit definitions for Debug Control Register 4.
DocID027809 Rev 4
e200z215An3 Core Debug Support
Description
Figure 991.
0 DAC1XM
(1)
- 0x0
=0, as well as unconditionally by m_por. If EDBCR0
EDM
DAC2XM DAC1CFG DAC2CFG
=1,
EDM
1665/2058
1719