Tx Controller Clocks - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
The LFAST block will know which of the phases will be required for the different modes of
operations. Therefore, the LFAST block will provide enables and speed mode switches to
the Clocking Module. The Clocking Module will use these signals to control the enables to
the clock phases to reduce the power consumption.
47.10.3.2 Clock module requirements for low speed phases
47.10.3.2.1 Low speed
The low speed clock phases are generated in Clocking Module. These four phases are
required to sample the data correctly at Low Speed mode. The LFAST block will provide the
enable for the phases. The clock source for the low speed phases is SYSCLK. The Clocking
Module block will need to generate the 4 phases of low speed clock 90 degrees apart.
Using the Low Speed mode on the interface allows the polyphase generation logic to be
turned off and the requirement of high-speed-freq × 8 MHz clock from the PLL is not
needed.
47.10.4

Tx controller clocks

47.10.4.1 Clocking module requirements for speed phases
The low speed phase 0 clock is sourced from the lfast_sysclk and the high speed phase 0
clock is sourced from the PLL. See
Table 693. Rx clocks summary
Rx Speed mode
Low Speed
High Speed
Table 694. Tx clocks summary
Tx Speed mode
Low Speed
High Speed
Table 694.
DocID027809 Rev 4
Source
lfast_sysclk
PLL
Source
lfast_sysclk
PLL
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