Low-Power Mode (Sleep Mode) - STMicroelectronics SPC572L series Reference Manual

Embedded Flash Memory (MP55)
When enabled the Flash Memory module returns to its pre-disable state in all cases unless
in the process of executing an Erase or a Program High Voltage operation at the time of
disable. If the Flash Memory module is disabled during an Erase operation, the operation is
suspended and MCR[ESUS] bits are set to '1'. The user may resume the Erase operation at
the time the module is enabled by clearing MCR[ESUS]. MCR[EHV] must be high to
resume the Erase operation.
If the Flash Memory module is disabled during a program operation, the operation is
suspended and MCR[PSUS] is set to '1'. The user may resume the program operation at
the time the module is enabled by clearing MCR[PSUS]. MCR[EHV] must be high to resume
the Erase operation.
If the Flash Memory module is disabled during an erase-suspended program operation, the
program operation is suspended and both ESUS and PSUS are set to a '1'. When the
module is enabled PSUS must be cleared first to resume the program. Erase may be
resumed after the program ends. EHV must be high to resume both operations.
If the Flash Memory module is disabled during AIC or MR, the operation is aborted and the
MISR value is not deterministic.
If the Flash Memory module is put in Power-down mode and the Vector Table remains
mapped in the Flash Address space, the user must be mindful that the Flash Memory
module significantly increases the interrupt response time by adding several Wait States.
Note: Do not enter Low-power mode when the Power-down mode is active.
29.4.3

Low-power mode (Sleep mode)

The Low-power (or Sleep) mode turns-off most of the DC current sources within the Flash
Memory module. Wake-up time from Low-power mode is faster than wake-up time from
Power-down mode.
In Low-power mode no Read from or Write to the Flash array is possible. Every Read
access executed when the Low-power mode is active outputs invalid data.
The user may not read some registers (UM0–UM9 and part of UT0) until the Low-power
mode is exited. Write access is locked on all the registers in Low-power mode.
When exiting from Low-power mode the Flash Memory module returns to its pre-sleep state
in all cases unless in the process of executing an Erase High Voltage operation at the time
of entering sleep mode. If the Flash Memory module is put in sleep mode during an Erase
operation, MCR[ESUS] is set to '1'. The user may resume the Erase operation at the time
the module exits from sleep by clearing MCR[ESUS]. MCR[EHV] must be high to resume
the Erase operation.
If the Flash Memory module is put in Low-power mode during a program operation, the
operation is suspended and MCR[PSUS] is set to '1'. The user may resume the program
operation at the time the module is enabled by clearing MCR[PSUS]. MCR[EHV] must be
high to resume the Erase operation.
If the Flash Memory module is put in Low-power mode during an erase-suspended program
operation, the program operation is suspended and both ESUS and PSUS are set to '1'.
When the module is enabled, PSUS must first be cleared for the program to resume. The
Erase may be resumed after the program ends. EHV must be high to resume both
operations.
If the Flash Memory module is disabled during AIC or MR, the operation is aborted and the
MISR value is not deterministic.
630/2058 DocID027809 Rev 4
RM0400