Figure 514. Message Ram Configuration - STMicroelectronics SPC572L series Reference Manual

RM0400
Start Address
SIDFC[FLSSA]
XIDFC[FLESA]
RXF0C[F0SA]
RXF1C[F1SA]
RXBC[RBSA]
TXEFC[EFSA]
TXBC[TBSA]
When the M_CAN addresses the Message RAM it addresses 32-bit words, not single bytes.
The configured start addresses are 32-bit word addresses.
Note: The M_CAN does not check for erroneous configuration of the Message RAM. Especially
the configuration of the start addresses of the different sections and the number of elements
of each section has to be done carefully to avoid falsification or loss of data.
44.3.6.1 Rx Buffer and FIFO element
Up to 64 Rx Buffers and two Rx FIFOs can be configured in the Message RAM. Each Rx
FIFO section can be configured to store up to 64 received messages. The structure of a Rx
Buffer / FIFO element is shown in the following figure.
31
R0
R1 FIDX[6:0]
R2 DB3[7:0]
R3 DB7[7:0]

Figure 514. Message RAM Configuration

11-bit Filter
29-bit Filter
Rx FIFO 0
Rx FIFO 1
Rx Buffers
Tx Event FIFO
Tx Buffers
32 bits
Figure 515. Rx FIFO Element
24 23
DLC[3:0]
DB2[7:0]
DB6[7:0]
DocID027809 Rev 4
0-128 elements / 0-128 words
0-64 elements / 0-128 words
0-64 elements / 0-256 words
0-64 elements / 0-244 words
0-64 elements / 0-256 words
0-32 elements / 0-64 words
0-32 elements / 0-128 words
16 15
ID[28:0]
DB1[7:0]
DB5[7:0]
CAN Subsystem
max. 1216 words
8 7
RXTS[15:0]
DB0[7:0]
DB4[7:0]
1047/2058
0
1091