STMicroelectronics SPC572L series Reference Manual page 69

RM0400
Figure 99. Write, pending read (2:1 timing mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Figure 100. Burst4 read (2:1 timing mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 101. Burst4 write (2:1 timing mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 102. Read, pending read (1:2 timing mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 103. Write, pending read (1:2 timing mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 104. Burst4 read (1:2 timing mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 105. Burst4 write (1:2 timing mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 106. Block diagram for an INTC with four processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 107. INTC Block Configuration Register (INTC_BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 108. INTC Current Priority Register for Processor n (INTC_CPRn) . . . . . . . . . . . . . . . . . . . . . 363
Figure 109. INTC Interrupt Acknowledge Register for Processor n (INTC_IACKRn) . . . . . . . . . . . . . 363
Figure 110. INTC End of Interrupt Register for Processor n (INTC_EOIRn) . . . . . . . . . . . . . . . . . . . . 364
Figure 111. INTC Software Set/Clear Interrupt Registers (INTC_SSCIRn) . . . . . . . . . . . . . . . . . . . . . 365
Figure 112. INTC Priority Select Register 0 (INTC_PSR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Figure 113. INTC Priority Select Register 1023 (INTC_PSR1023) . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 114. Timing diagram of software vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Figure 115. Timing diagram for hardware vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 116. Interrupt request block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Figure 117. Timing diagram of raised priority preserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 118. eDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Figure 119. Control Register (DMA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Figure 120. Error Status Register (DMA_ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Figure 121. Enable Request Register Low (DMA_ERQL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 122. Enable Error Interrupt Register Low (DMA_EEIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Figure 123. Set Enable Request Register (DMA_SERQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 124. Clear Enable Request Register (DMA_CERQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Figure 125. Set Enable Error Interrupt Register (DMA_SEEI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Figure 126. Clear Enable Error Interrupt Register (DMA_CEEI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Figure 127. Clear Interrupt Request Register (DMA_CINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Figure 128. Clear Error Register (DMA_CERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Figure 129. Set START Bit Register (DMA_SSRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 130. Clear DONE Status Bit Register (DMA_CDNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Figure 131. Interrupt Request Register Low (DMA_INTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 132. Error Register Low (DMA_ERRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 133. Hardware Request Status Register Low (DMA_HRSL) . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Figure 134. Channel n Priority Register (DMA_DCHPRIn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 135. Channel n Master ID Register (DMA_DCHMIDn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Figure 136. TCD Source Address (DMA_TCDn_SADDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 137. TCD Transfer Attributes (DMA_TCDn_ATTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 138. TCD Signed Source Address Offset (DMA_TCDn_SOFF). . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 139. TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO) . . . . . . . 419
Figure 140. TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Figure 141. TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Figure 142. TCD Last Source Address Adjustment (DMA_TCDn_SLAST) . . . . . . . . . . . . . . . . . . . . . 421
Figure 143. TCD Destination Address (DMA_TCDn_DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Figure 144. TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Figure 145. TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Figure 146. TCD Signed Destination Address Offset (DMA_TCDn_DOFF) . . . . . . . . . . . . . . . . . . . . 424
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